EP2AGX65DF29C6N Altera, EP2AGX65DF29C6N Datasheet - Page 65

• Manufacturer Part Number: EP2AGX65DF29C6N
• Description: IC ARRIA II GX FPGA 65K 780FBGA
• Manufacturer: Altera
• Series: Arria II GXr

Specifications of EP2AGX65DF29C6N

• Number Of Logic Elements/cells: 60214
• Number Of Labs/clbs: 2530
• Total Ram Bits: 5246
• Number Of I /o: 364
• Voltage - Supply: 0.87 V ~ 0.93 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 780-FBGA
• Family Name: Arria® II GX
• Number Of Logic Blocks/elements: 63250
• # I/os (max): 364
• Frequency (max): 400MHz
• Operating Supply Voltage (typ): 900mV
• Logic Cells: 63250
• Ram Bits: 5557452.8
• Operating Supply Voltage (min): 0.87V
• Operating Supply Voltage (max): 0.93V
• Operating Temp Range: 0C to 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 780
• Package Type: FC-FBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Compliant

Chapter 1: Device Datasheet for Arria II Devices
Switching Characteristics
Table 1–41. Transceiver Block Jitter Specifications for Arria II GZ Devices
December 2010 Altera Corporation
OBSAI Transmit Jitter Generation
Total jitter at 768 Mbps,
1536 Mbps, and 3072 Mbps
Deterministic jitter at
768 MBps, 1536 Mbps, and
3072 Mbps
OBSAI Receiver Jitter Tolerance
Deterministic jitter tolerance
at 768 Mbps, 1536 Mbps,
and 3072 Mbps
Combined deterministic and
random jitter tolerance at
768 Mbps, 1536 Mbps, and
3072 Mbps
Sinusoidal jitter tolerance at
768 Mbps
Sinusoidal jitter tolerance at
1536 Mbps
Sinusoidal jitter tolerance at
3072 Mbps
Notes to
(1) Dedicated refclk pins were used to drive the input reference clocks.
(2) The jitter numbers are valid for the stated conditions only.
(3) The jitter numbers for SONET/SDH are compliant to the GR-253-CORE Issue 3 Specification.
(4) The jitter numbers for XAUI are compliant to the IEEE802.3ae-2002 Specification.
(5) The jitter numbers for PCIe are compliant to the PCIe Base Specification 2.0.
(6) The jitter numbers for Serial RapidIO are compliant to the RapidIO Specification 1.3.
(7) The jitter numbers for GIGE are compliant to the IEEE802.3-2002 Specification.
(8) Arria II GZ PCIe receivers are compliant to this specification provided the V
(9) The jitter numbers for Serial Attached SCSI (SAS) are compliant to the SAS-2.1 Specification.
(10) The jitter numbers for CPRI are compliant to the CPRI Specification V3.0.
(11) The jitter numbers for OBSAI are compliant to the OBSAI RP3 Specification V4.1.
Table
Description
Symbol/
1–40:
1843.2 MHz to 20 MHz
921.6 MHz to 20 MHz
REFCLK = 153.6 MHz
REFCLK = 153.6 MHz
460 MHz to 20 MHz
(11)
Jitter frequency =
Jitter frequency =
Jitter frequency =
Jitter frequency =
Jitter frequency =
Jitter frequency =
(11)
Pattern = CJPAT
Pattern = CJPAT
Pattern = CJPAT
Pattern = CJPAT
Pattern = CJPAT
Pattern = CJPAT
Pattern = CJPAT
Pattern = CJPAT
Pattern CJPAT
Pattern CJPAT
Conditions
10.9 KHz
21.8 KHz
5.4 KHz
Min
—
—
TX-CM-DC-ACTIVEIDLE-DELTA
Arria II Device Handbook Volume 3: Device Datasheet and Addendum
–C3 and –I3
Typ
> 0.37
> 0.55
—
—
> 8.5
> 0.1
> 8.5
> 0.1
> 8.5
> 0.1
(Note
Max
0.35
0.17
1),
of the upstream transmitter is less than 50 mV.
(2)
Min
—
—
(Part 8 of 8)
–C4 and –I4
> 0.37
> 0.55
Typ
—
—
> 8.5
> 0.1
> 8.5
> 0.1
> 8.5
> 0.1
0.35
0.17
Max
Unit
UI
UI
UI
UI
UI
UI
UI
UI
UI
UI
1–57