EP2AGX65DF29C6N Altera, EP2AGX65DF29C6N Datasheet - Page 76

• Manufacturer Part Number: EP2AGX65DF29C6N
• Description: IC ARRIA II GX FPGA 65K 780FBGA
• Manufacturer: Altera
• Series: Arria II GXr

Specifications of EP2AGX65DF29C6N

• Number Of Logic Elements/cells: 60214
• Number Of Labs/clbs: 2530
• Total Ram Bits: 5246
• Number Of I /o: 364
• Voltage - Supply: 0.87 V ~ 0.93 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 780-FBGA
• Family Name: Arria® II GX
• Number Of Logic Blocks/elements: 63250
• # I/os (max): 364
• Frequency (max): 400MHz
• Operating Supply Voltage (typ): 900mV
• Logic Cells: 63250
• Ram Bits: 5557452.8
• Operating Supply Voltage (min): 0.87V
• Operating Supply Voltage (max): 0.93V
• Operating Temp Range: 0C to 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 780
• Package Type: FC-FBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Compliant

1–68
Table 1–53. High-Speed I/O Specifications for Arria II GX Devices (Part 3 of 3)
Arria II Device Handbook Volume 3: Device Datasheet and Addendum
t
TCCS
Receiver
True differential
I/O standards -
f
rate)
f
Soft-CDR PPM
tolerance
DPA run length
Sampling
window (SW)
Notes to
(1) f
(2) This applies to interfacing with DPA receivers. For interfacing with non-DPA receivers, the maximum supported data rate is 945 Mbps. Beyond
(3) The minimum and maximum specification depends on the clock source (for example, PLL and clock pin) and the clock routing resource you
(4) The specification is only applicable under the influence of core noise.
(5) Specification is only applicable for true LVDS using dedicated SERDES.
(6) Dedicated SERDES and DPA features are only available on the right banks.
(7) You are required to calculate the leftover timing margin in the receiver by performing link timing closure analysis. You must consider the board
RISE
HSDRDPA
HSDR
840 Mbps, PCB trace compensation is required. PCB trace compensation refers to the adjustment of the PCB trace length for LVDS channels
to improve channel-to-channel skews and is required to support date rates beyond 840 Mbps.
use (global, regional, or local). The I/O differential buffer and input register do not have a minimum toggle rate.
skew margin, transmitter channel-to-channel skew, and the receiver sampling margin to determine the leftover timing margin.
and t
HSCLK_IN
Symbol
(data rate)
Table
(data
FALL
(6)
= f
1–53:
HSDR
/ W. Use W to determine the supported selection of input reference clock frequencies for the desired data rate.
Non-DPA mode
SERDES factor
SERDES factor
SERDES factor
DDR registers)
SERDES factor
True LVDS and
True LVDS
SDR registers)
LVDS_E_3R
LVDS_E_3R
J = 2 (using
J = 1 (using
Conditions
J = 3 to 10
J = 3 to 10
DPA mode
Soft-CDR
Emulated
emulated
mode
(5)
(5)
Min
150
—
—
—
—
—
—
(3)
(3)
(3)
I3
10,000
1250
Max
200
150
200
945
300
300
(7)
(7)
(7)
Min
150
—
—
—
—
—
—
(3)
(3)
(3)
C4
10,000
1250
Max
200
150
200
945
300
300
(7)
(7)
(7)
Min
150
—
—
—
(3)
(3)
(3)
—
—
—
Chapter 1: Device Datasheet for Arria II Devices
C5,I5
10,000
1050
Max
225
175
250
740
300
350
(7)
(7)
(7)
December 2010 Altera Corporation
Min
150
—
—
—
—
—
—
(3)
(3)
(3)
Switching Characteristics
C6
10,000
Max
840
250
200
300
640
300
400
(7)
(7)
(7)
PPM
Mbps
Mbps
Mbps
Mbps
Unit
ps
ps
ps
UI
ps