EP1S25F672C8 Altera, EP1S25F672C8 Datasheet - Page 40

IC STRATIX FPGA 25K LE 672-FBGA

EP1S25F672C8

Manufacturer Part Number
EP1S25F672C8
Description
IC STRATIX FPGA 25K LE 672-FBGA
Manufacturer
Altera
Series
Stratix®r
Datasheet

Specifications of EP1S25F672C8

Number Of Logic Elements/cells
25660
Number Of Labs/clbs
2566
Total Ram Bits
1944576
Number Of I /o
473
Voltage - Supply
1.425 V ~ 1.575 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
672-FBGA
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Number Of Gates
-
Other names
544-1119

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TriMatrix Memory
Figure 2–14. Shift Register Memory Configuration
2–26
Stratix Device Handbook, Volume 1
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w × m × n Shift Register
m-Bit Shift Register
m-Bit Shift Register
m-Bit Shift Register
m-Bit Shift Register
Memory Block Size
TriMatrix memory provides three different memory sizes for efficient
application support. The large number of M512 blocks are ideal for
designs with many shallow first-in first-out (FIFO) buffers. M4K blocks
provide additional resources for channelized functions that do not
require large amounts of storage. The M-RAM blocks provide a large
single block of RAM ideal for data packet storage. The different-sized
blocks allow Stratix devices to efficiently support variable-sized memory
in designs.
The Quartus II software automatically partitions the user-defined
memory into the embedded memory blocks using the most efficient size
combinations. You can also manually assign the memory to a specific
block size or a mixture of block sizes.
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Altera Corporation
n Number
of Taps
July 2005

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