EP20K400EFC672-2 | |
|---|---|
| Manufacturer Part Number | EP20K400EFC672-2 |
| Description | IC APEX 20KE FPGA 400K 672-FBGA |
| Manufacturer | Altera |
| Series | APEX-20K® |
| EP20K400EFC672-2 datasheets |
|
Availability: In stock
International delivery:
Warranty: 60 days
×
- We provide standard 60-days warranty for all parts. If warranty differs we always mention it beforehand. In case of return we cover shipping costs.
- If you still have any questions - please contact us
×
Shipping terms
- Standard delivery time differs from 5-8 business days if the supplier is a local one to 12-14 days if the suplier is from overseas. If delivery time differs it's always mentioned in our quotation.
- We ship worldwide using main international couriers like FedEx, DHL, UPS, TNT, EMS. We can also use client's freight account. Other shipping methods can be discussed. We do best to meet your needs!
Payment terms
- For new client payment term is payment in advance. At this moment we accept 3 payment methods: wire transfer, PayPal and Western Union. Credit card payment is under constrution and will be introduced soon. Escrow service is acceptable. Net terms for regular customers is not a problem. Working with us is totally safe for you.
- If you still have any questions - please contact us
Specifications of EP20K400EFC672-2 | |||
|---|---|---|---|
| Number Of Logic Elements/cells | 16640 | Number Of Labs/clbs | 1664 |
| Total Ram Bits | 212992 | Number Of I /o | 488 |
| Number Of Gates | 1052000 | Voltage - Supply | 1.71 V ~ 1.89 V |
| Mounting Type | Surface Mount | Operating Temperature | 0°C ~ 85°C |
| Package / Case | 672-FBGA | Lead Free Status / RoHS Status | Contains lead / RoHS non-compliant |
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
PrevNext
APEX 20K Programmable Logic Device Family Data Sheet
Implementing Logic in ROM
In addition to implementing logic with product terms, the ESB can
implement logic functions when it is programmed with a read-only
pattern during configuration, creating a large LUT. With LUTs,
combinatorial functions are implemented by looking up the results, rather
than by computing them. This implementation of combinatorial functions
can be faster than using algorithms implemented in general logic, a
performance advantage that is further enhanced by the fast access times of
ESBs. The large capacity of ESBs enables designers to implement complex
functions in one logic level without the routing delays associated with
linked LEs or distributed RAM blocks. Parameterized functions such as
LPM functions can take advantage of the ESB automatically. Further, the
Quartus II software can implement portions of a design with ESBs where
appropriate.
Programmable Speed/Power Control
APEX 20K ESBs offer a high-speed mode that supports very fast operation
on an ESB-by-ESB basis. When high speed is not required, this feature can
be turned off to reduce the ESB’s power dissipation by up to 50%. ESBs
that run at low power incur a nominal timing delay adder. This
TM
Turbo Bit
option is available for ESBs that implement product-term
logic or memory functions. An ESB that is not used will be powered down
so that it does not consume DC current.
Designers can program each ESB in the APEX 20K device for either
high-speed or low-power operation. As a result, speed-critical paths in the
design can run at high speed, while the remaining paths operate at
reduced power.
I/O Structure
The APEX 20K IOE contains a bidirectional I/O buffer and a register that
can be used either as an input register for external data requiring fast setup
times, or as an output register for data requiring fast clock-to-output
performance. IOEs can be used as input, output, or bidirectional pins. For
fast bidirectional I/O timing, LE registers using local routing can improve
setup times and OE timing. The Quartus II software Compiler uses the
programmable inversion option to invert signals from the row and column
interconnect automatically where appropriate. Because the APEX 20K IOE
offers one output enable per pin, the Quartus II software Compiler can
emulate open-drain operation efficiently.
The APEX 20K IOE includes programmable delays that can be activated to
ensure zero hold times, minimum clock-to-output times, input IOE
register-to-core register transfers, or core-to-output IOE register transfers.
A path in which a pin directly drives a register may require the delay to
ensure zero hold time, whereas a path in which a pin drives a register
through combinatorial logic may not require the delay.
Altera Corporation
37
Related parts for EP20K400EFC672-2 | |||
|---|---|---|---|
| Part Number | Description | Manufacturer | Datasheet |
 EP20K400EFC672-3 |
Altera Corporation | ||
|
EP20K400EFC672-1 |
Altera Corporation | ||
|
EP20K400EFC6721N |
BGA | Altera Corporation | |
|
EP20K400EFI6722X |
BGA672 | Altera Corporation |
|
 EP20K400EFC672-2N |
IC APEX 20KE FPGA 400K 672-FBGA | Altera |
|
|
EP20K400EFC672-2X |
IC APEX 20KE FPGA 400K 672-FBGA | Altera |
|
|
EP20K400EFC672-1X |
IC APEX 20KE FPGA 400K 672-FBGA | Altera |
|
|
EP20K400EFI672-2X |
IC APEX 20KE FPGA 400K 672-FBGA | Altera |
|
|
EP20K400EFC672-1XN |
IC APEX 20KE FPGA 400K 672-FBGA | Altera |
|
 EP20K400EFI672-2N |
APEX 20KE | Altera |
|
|
EP20K400EFC672-3N |
IC APEX 20KE FPGA 400K 672-FBGA | Altera |
|
|
EP20K400EFC672-1N |
APEX 20KE | Altera | |
|
EP20K400EBC356-2 |
Altera Corporation | ||
|
EP20K400EBC652-3 |
Altera Corporation | ||
|
EP20K400EBC6522X |
BGA | Altera Corporation | |
