EP1S30F1020C6 Altera, EP1S30F1020C6 Datasheet - Page 195

• Manufacturer Part Number: EP1S30F1020C6
• Description: IC STRATIX FPGA 30K LE 1020-FBGA
• Manufacturer: Altera
• Series: Stratix®r

Specifications of EP1S30F1020C6

• Number Of Logic Elements/cells: 32470
• Number Of Labs/clbs: 3247
• Total Ram Bits: 3317184
• Number Of I /o: 726
• Voltage - Supply: 1.425 V ~ 1.575 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 1020-FBGA
• Family Name: Stratix
• Number Of Logic Blocks/elements: 32470
• # I/os (max): 726
• Frequency (max): 450.05MHz
• Process Technology: 0.13um (CMOS)
• Operating Supply Voltage (typ): 1.5V
• Logic Cells: 32470
• Ram Bits: 3317184
• Operating Supply Voltage (min): 1.425V
• Operating Supply Voltage (max): 1.575V
• Operating Temp Range: 0C to 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 1020
• Package Type: FC-FBGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Not Compliant
• Other names: 544-1419; EP1S30SF1020C6

Altera Corporation
January 2006
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M4KDATAAH
M4KADDRASU
M4KADDRAH
M4KDATABSU
M4KDATABH
M4KADDRBSU
M4KADDRBH
M4KDATACO1
M4KDATACO2
M4KCLKHL
M4KCLR
MRAMRC
MRAMWC
MRAMWERESU
MRAMWEREH
MRAMCLKENSU
MRAMCLKENH
MRAMBESU
MRAMBEH
MRAMDATAASU
MRAMDATAAH
MRAMADDRASU
MRAMADDRAH
MRAMDATABSU
Table 4–41. M4K Block Internal Timing Microparameter Descriptions (Part
2 of 2)
Table 4–42. M-RAM Block Internal Timing Microparameter
Descriptions (Part 1 of 2)
Symbol
Symbol
A port data hold time after clock
A port address setup time before clock
A port address hold time after clock
B port data setup time before clock
B port data hold time after clock
B port address setup time before clock
B port address hold time after clock
Clock-to-output delay when using output registers
Clock-to-output delay without output registers
Register minimum clock high or low time. This is a limit on
the min time for the clock on the registers in these blocks.
The actual performance is dependent upon the internal
point-to-point delays in the blocks and may give slower
performance as shown
reported by the timing analyzer in the Quartus II software.
Minimum clear pulse width
Synchronous read cycle time
Synchronous write cycle time
Write or read enable setup time before clock
Write or read enable hold time after clock
Clock enable setup time before clock
Clock enable hold time after clock
Byte enable setup time before clock
Byte enable hold time after clock
A port data setup time before clock
A port data hold time after clock
A port address setup time before clock
A port address hold time after clock
B port setup time before clock
Stratix Device Handbook, Volume 1
inTable 4–36 on page 4–20
Parameter
Parameter
DC & Switching Characteristics
and as
4–25