XC5VLX50T-1FFG1136C Xilinx Inc, XC5VLX50T-1FFG1136C Datasheet - Page 55

IC FPGA VIRTEX-5 50K 1136FBGA

XC5VLX50T-1FFG1136C

Manufacturer Part Number
XC5VLX50T-1FFG1136C
Description
IC FPGA VIRTEX-5 50K 1136FBGA
Manufacturer
Xilinx Inc
Series
Virtex™-5 LXTr

Specifications of XC5VLX50T-1FFG1136C

Total Ram Bits
2211840
Number Of Logic Elements/cells
46080
Number Of Labs/clbs
3600
Number Of I /o
480
Voltage - Supply
0.95 V ~ 1.05 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
1136-BBGA, FCBGA
No. Of Logic Blocks
7200
No. Of Gates
50000
Family Type
Virtex-5 LXT
No. Of Speed Grades
1
No. Of I/o's
480
Clock Management
PLL
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
HW-V5-ML561-UNI-G - EVALUATION PLATFORM VIRTEX-5HW-V5-ML550-UNI-G - EVALUATION PLATFORM VIRTEX-5HW-V5-ML521-UNI-G - EVALUATION PLATFORM VIRTEX-5HW-V5GBE-DK-UNI-G - KIT DEV V5 LXT GIGABIT ETHERNET122-1508 - EVALUATION PLATFORM VIRTEX-5
Number Of Gates
-
Lead Free Status / RoHS Status
Lead free / RoHS Compliant, Lead free / RoHS Compliant
Other names
122-1564
PLL Switching Characteristics
Table 74: PLL Specification
Symbol
F
Maximum Input Clock Frequency
INMAX
F
Minimum Input Clock Frequency
INMIN
F
Maximum Input Clock Period Jitter
INJITTER
F
Allowable Input Duty Cycle: 19—49 MHz
INDUTY
Allowable Input Duty Cycle: 50—199 MHz
Allowable Input Duty Cycle: 200—399 MHz
Allowable Input Duty Cycle: 400—499 MHz
Allowable Input Duty Cycle: >500 MHz
F
Minimum PLL VCO Frequency
VCOMIN
F
Maximum PLL VCO Frequency
VCOMAX
F
Low PLL Bandwidth at Typical
BANDWIDTH
High PLL Bandwidth at Typical
T
Static Phase Offset of the PLL Outputs
STAPHAOFFSET
T
PLL Output Jitter
OUTJITTER
T
PLL Output Clock Duty Cycle Precision
OUTDUTY
T
PLL Maximum Lock Time
LOCKMAX
PLL Maximum Output Frequency for LX20T devices
PLL Maximum Output Frequency for LX30, LX30T, LX50,
LX50T, LX85, LX85T, LX110, LX110T, SX35T, SX50T, FX30T,
and FX70Tdevices
PLL Maximum Output Frequency for LX155, LX155T, and
F
OUTMAX
FX100T devices
PLL Maximum Output Frequency for FX130T devices
PLL Maximum Output Frequency for LX220, LX220T, LX330,
LX330T, SX95T, SX240T, TX150T, TX240T, and FX200T
devices
F
PLL Minimum Output Frequency
OUTMIN
T
External Clock Feedback Variation
EXTFDVAR
RST
Minimum Reset Pulse Width
MINPULSE
F
Maximum Frequency at the Phase Frequency Detector
PFDMAX
F
Minimum Frequency at the Phase Frequency Detector
PFDMIN
T
Maximum External Delay in the Feedback Path
FBDELAY
Notes:
1.
The PLL does not filter typical spread spectrum input clocks because they are usually far below the bandwidth filter frequencies.
2.
Values for this parameter are available in the Architecture Wizard.
3.
Includes global clock buffer.
4.
The LOCK signal must be sampled after T
expired.
5.
Calculated as F
/128 assuming output duty cycle is 50%.
VCO
DS202 (v5.3) May 5, 2010
Product Specification
Virtex-5 FPGA Data Sheet: DC and Switching Characteristics
Description
(1)
(1)
(2)
(3)
(4)
(5)
. The LOCK signal is invalid after configuration or reset until the T
LOCKMAX
www.xilinx.com
Speed Grade
Units
-3
-2
-1
710
710
645
MHz
19
19
19
MHz
<20% of clock input period or 1 ns Max
25/75
%
30/70
%
35/65
%
40/60
%
45/55
%
400
400
400
MHz
1440
1200
1000
MHz
1
1
1
MHz
4
4
4
MHz
120
120
120
ps
Note 1
±150
±200
±200
ps
100
100
100
µs
N/A
667
600
MHz
710
667
600
MHz
650
600
550
MHz
550
500
450
MHz
N/A
500
450
MHz
3.125
3.125
3.125
MHz
< 20% of clock input period or 1 ns Max
5
5
5
ns
550
500
450
MHz
19
19
19
MHz
3 ns Max or one CLKIN cycle
time has
LOCKMAX
55

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