XC6VCX75T-1FFG784I Xilinx Inc, XC6VCX75T-1FFG784I Datasheet - Page 39

• Manufacturer Part Number: XC6VCX75T-1FFG784I
• Description: IC FPGA VIRTEX 6 74K 784FFGBGA
• Manufacturer: Xilinx Inc
• Series: Virtex™ 6 CXTr

Specifications of XC6VCX75T-1FFG784I

• Number Of Logic Elements/cells: 74496
• Number Of Labs/clbs: 5820
• Total Ram Bits: 5750784
• Number Of I /o: 360
• Voltage - Supply: 0.95 V ~ 1.05 V
• Mounting Type: Surface Mount
• Operating Temperature: -40°C ~ 100°C
• Package / Case: 784-BBGA, FCBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -

DSP48E1 Switching Characteristics
Table 51: DSP48E1 Switching Characteristics
DS153 (v1.6) February 11, 2011
Product Specification
Setup and Hold Times of Data/Control Pins to the Input Register Clock
T
T
T
T
Setup and Hold Times of Data Pins to the Pipeline Register Clock
T
T
T
Setup and Hold Times of Data/Control Pins to the Output Register Clock
T
T
T
T
T
T
T
T
Setup and Hold Times of the CE Pins
T
T
T
T
T
T
Setup and Hold Times of the RST Pins
T
T
T
T
T
T
Combinatorial Delays from Input Pins to Output Pins
T
T
T
T
DSPDCK_{A, ACIN; B, BCIN}_{AREG; BREG}
DSPCKD_{A, ACIN; B, BCIN}_{AREG; BREG}
DSPDCK_C_CREG
DSPDCK_D_DREG
DSPDCK_{A, ACIN, B, BCIN}_PREG_MULT
DSPCKD_{A, ACIN, B, BCIN}_PREG_MULT
DSPDCK_{A, D}_ADREG
DSPDCK_{A, ACIN, B, BCIN}_PREG_MULT
DSPCKD_{A, ACIN, B, BCIN}_PREG_MULT
DSPDCK_D_DREG_MULT
DSPDCK_{A, ACIN, B, BCIN}_PREG
DSPCKD_{A, ACIN, B, BCIN}_PREG
DSPDCK_C_PREG
DSPDCK_{PCIN, CARRYCASCIN, MULTSIGNIN}_PREG
DSPCKD_{PCIN, CARRYCASCIN, MULTSIGNIN}_PREG
DSPDCK_{CEA; CEB}_{AREG; BREG}
DSPCKD_{CEA; CEB}_{AREG; BREG}
DSPDCK_CEC_CREG
DSPDCK_CED_DREG
DSPDCK_CEM_MREG
DSPDCK_CEP_PREG
DSPDCK_{RSTA; RSTB}_{AREG; BREG}
DSPCKD_{RSTA; RSTB}_{AREG; BREG}
DSPDCK
DSPDCK
DSPDCK
DSPDCK
DSPDO_{A, B}_{P, CARRYOUT}_MULT
DSPDO_D_{P, CARRYOUT}_MULT
DSPDO_{A, B}_{P, CARRYOUT}
DSPDO_{C, CARRYIN}_{P, CARRYOUT}
_RSTC_CREG
_RSTD_DREG
_RSTM_MREG
_RSTP_PREG
/ T
/T
/T
DSPCKD_C_CREG
DSPCKD_D_DREG
/ T
DSPCKD_C_PREG
/ T
/ T
/ T
Symbol
/ T
/ T
/ T
/ T
DSPCKD_CEP_PREG
/ T
DSPCKD_CEC_CREG
DSPCKD_CED_DREG
DSPCKD_CEM_MREG
/ T
DSPCKD
DSPCKD
DSPCKD
DSPCKD
DSPCKD
DSPCKD_D_DREG_MULT
/
_
_RSTP_PREG
_RSTC_CREG
_RSTD_DREG
/
_RSTM_MREG
{A, D}_ADREG
/
/
/
/
/
{A, ACIN, B, BCIN} input to {A, B} register CLK
C input to C register CLK
D input to D register CLK
{A, ACIN, B, BCIN} input to M register CLK
{A, D} input to AD register CLK
{A, ACIN, B, BCIN} input to P register CLK using
multiplier
D input to P register CLK
{A, ACIN, B, BCIN} input to P register CLK not
using multiplier
C input to P register CLK
{PCIN, CARRYCASCIN, MULTSIGNIN} input to
P register CLK
{CEA; CEB} input to {A; B} register CLK
CEC input to C register CLK
CED input to D register CLK
CEM input to M register CLK
CEP input to P register CLK
{RSTA, RSTB} input to {A, B} register CLK
RSTC input to C register CLK
RSTD input to D register CLK
RSTM input to M register CLK
RSTP input to P register CLK
{A, B} input to {P, CARRYOUT} output using
multiplier
D input to {P, CARRYOUT} output using
multiplier
{A, B} input to {P, CARRYOUT} output not using
multiplier
{C, CARRYIN} input to {P, CARRYOUT} output
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Description
Virtex-6 CXT Family Data Sheet
5.20/–0.19 5.97/–0.22
4.90/–0.65 5.63/–0.75
2.15/–0.19 2.47/–0.22
1.91/–0.14 2.19/–0.17
1.67/–0.04 1.92/–0.05
0.35/0.34
0.22/0.24
0.15/0.39
3.21/0.02
1.69/0.13
0.22/0.25
0.24/0.23
0.31/0.14
0.26/0.25
0.46/0.03
0.38/0.22
0.23/0.09
0.38/0.19
0.26/0.30
0.33/0.05
5.08
4.82
2.07
1.83
-2
Speed Grade
0.41/0.39
0.26/0.27
0.17/0.44
3.69/0.02
1.94/0.15
0.25/0.29
0.28/0.27
0.35/0.16
0.30/0.28
0.53/0.03
0.43/0.25
0.27/0.11
0.44/0.21
0.30/0.35
0.41/0.06
5.84
5.54
2.38
2.10
-1
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
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