XC6VCX75T-1FFG784I Xilinx Inc, XC6VCX75T-1FFG784I Datasheet - Page 43

• Manufacturer Part Number: XC6VCX75T-1FFG784I
• Description: IC FPGA VIRTEX 6 74K 784FFGBGA
• Manufacturer: Xilinx Inc
• Series: Virtex™ 6 CXTr

Specifications of XC6VCX75T-1FFG784I

• Number Of Logic Elements/cells: 74496
• Number Of Labs/clbs: 5820
• Total Ram Bits: 5750784
• Number Of I /o: 360
• Voltage - Supply: 0.95 V ~ 1.05 V
• Mounting Type: Surface Mount
• Operating Temperature: -40°C ~ 100°C
• Package / Case: 784-BBGA, FCBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -

Table 52: Configuration Switching Characteristics (Cont’d)
DS153 (v1.6) February 11, 2011
Product Specification
Notes:
1.
2.
3.
BPI Master Flash Mode Programming Switching
T
T
T
SPI Master Flash Mode Programming Switching
T
T
T
T
CCLK Output (Master Modes)
T
T
CCLK Input (Slave Modes)
T
T
Dynamic Reconfiguration Port (DRP) for MMCM Before and After DCLK
F
T
T
T
T
T
T
T
BPICCO
BPIDCC
INITADDR
SPIDCC
SPICCM
SPICCFC
FSINIT
MCCKL
MCCKH
SCCKL
SCCKH
DCK
MMCMDCK_DADDR
MMCMCKD_DADDR
MMCMDCK_DI
MMCMDCK_DEN
MMCMDCK_DWE
MMCMCKO_DO
MMCMCKO_DRDY
To support longer delays in configuration, use the design solutions described in Virtex-6 FPGA Configuration Guide.
Only during configuration, the last edge is determined by a weak pull-up/pull-down resistor in the I/O.
DO will hold until next DRP operation.
/T
/T
/T
(2)
FSINITH
BPICCD
SPIDCCD
/T
Symbol
MMCMCKD_DI
/T
/T
MMCMCKD_DEN
MMCMCKD_DWE
/
ADDR[25:0], RS[1:0], FCS_B, FOE_B, FWE_B outputs
valid after CCLK rising edge at 2.5V
ADDR[25:0], RS[1:0], FCS_B, FOE_B, FWE_B outputs
valid after CCLK rising edge at 1.8V
Setup/Hold on D[15:0] data input pins
Minimum period of initial ADDR[25:0] address cycles
DIN Setup/Hold before/after the rising CCLK edge
MOSI clock to out at 2.5V
MOSI clock to out at 1.8V
FCS_B clock to out at 2.5V
FCS_B clock to out at 1.8V
FS[2:0] to INIT_B rising edge Setup and Hold
Master CCLK clock Low time duty cycle
Master CCLK clock High time duty cycle
Slave CCLK clock minimum Low time
Slave CCLK clock minimum High time
Maximum frequency for DCLK
DADDR Setup/Hold
DI Setup/Hold
DEN Setup/Hold time
DWE Setup/Hold time
CLK to out of DO
CLK to out of DRDY
(3)
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Description
1.63/0.00 1.63/0.00
1.63/0.00 1.63/0.00
1.63/0.00 1.63/0.00
1.63/0.00 1.63/0.00
Virtex-6 CXT Family Data Sheet
4.0/0.0
3.0/0.0
45/55
45/55
3.64
0.38
200
2.5
2.5
Speed Grade
-2
6
6
3
6
6
6
6
2
4.0/0.0
3.0/0.0
45/55
45/55
3.64
0.38
200
2.5
2.5
-1
6
6
3
6
6
6
6
2
CCLK cycles
%, Min/Max
%, Min/Max
ns, Min
ns, Min
Units
MHz
ns
ns
ns
ns
ns
ns
ns
ns
µs
ns
ns
ns
ns
ns
ns
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