XC6VCX75T-1FFG784I Xilinx Inc, XC6VCX75T-1FFG784I Datasheet - Page 51

• Manufacturer Part Number: XC6VCX75T-1FFG784I
• Description: IC FPGA VIRTEX 6 74K 784FFGBGA
• Manufacturer: Xilinx Inc
• Series: Virtex™ 6 CXTr

Specifications of XC6VCX75T-1FFG784I

• Number Of Logic Elements/cells: 74496
• Number Of Labs/clbs: 5820
• Total Ram Bits: 5750784
• Number Of I /o: 360
• Voltage - Supply: 0.95 V ~ 1.05 V
• Mounting Type: Surface Mount
• Operating Temperature: -40°C ~ 100°C
• Package / Case: 784-BBGA, FCBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -

DS153 (v1.6) February 11, 2011
Product Specification
06/08/10
06/30/10
07/28/10
10/14/10
02/11/11
Date
Version
1.2
1.3
1.4
1.5
1.6
Revised
Added V
Added V
Updated
Removed DIFF SSTL15 and added values to SSTL15 in
Updated
Added
Updated entire
Changed specifications of PCI Express in
In
specifications.
Updated speed specification to v1.04 with appropriate changes to
Revised the IOB switching characteristics in
Updated values in
ILOGIC
characteristics changes.
Revised T
Revised CLB switching characteristics and added T
characteristics in
In
to ECCPARITY in standard ECC mode, revised T
revised F
Multiple changes to configuration specifications in
Revised switching characteristics and global clock tree (BUFG) F
Revised switching characteristics and I/O clock tree (BUFIO) F
Added note 1 to
Revised the F
Multiple changes to MMCM specifications in
Updated switching characteristics in
Removed T
Production release of XC6VCX130T and XC6VCX240T in
grade SDR values in
Table
Production release of XC6VCX75T and XC6VCX195T in
software with speed file v1.06 using the Speed File Patch. Updated PCI compliance on page 1. Added
values to
in
Table
Moved data sheet to Production status on the first page. Updated speed file with ISE 12.3 software with
speed file v1.08 using the Speed File Patch. In
CARRYCASCOUT, MULTSIGNOUT}_PREG
Updated
T
The following revisions are due to specification changes as described in XCN11009, Virtex-6 FPGA:
Data Sheet, User Guides, and JTAG ID Updates.
In
Specification, added bandwidth settings to F
BPICCO
Table
Table
Table
Table
57.
61,
eFUSE Read Endurance
(Table
35, removed RLDRAM II and revised and added values to other interface performance
50, removed T
53,
52, updated the values for T
GTX Transceivers in CXT Devices, page
FS
FS
values in
Table 13
Table 16
MAX
Table 10
Table
Table
IODELAY_CLK_MAX
and note 6 to
DCD_BUFH
and revised the V
Table
and F
MAX
42), OLOGIC
13. In
GTX Transceivers in CXT Devices
62, and
Table
Table 48
54, and
including adding note 2.
through
to include the industrial range specifications. Added Note 12 to
horizontal clock tree (BUFH) in
Table
Table 39
MAX_CASCADE
Table
Table
and T
55.
RCKO_RDCOUNT
Table
52. Updated range description for F
Table
www.xilinx.com
Table
Table
and
35. Updated BUFIO F
25, update V
and note 4 in
and T
BUFHSKEW
(Table
IN
63.
Table
10. Revised description of C
and V
56. Updated F
19.
section.
IDELAYPAT_JIT
switching characteristics.
43), ISERDES
.
Table 58
SMCCKW
Description of Revisions
49.
TS
and T
from
CMOUTDC
values in
Table
Table
Table
RCKO_WRCOUNT
PFDMIN
Table
, T
Table 57
through
INMAX
in
Table
SPIDCC
41.
34.
MAX
RDCK_DI_ECC
Table
equation to MGTAVTT – DV
5.
Table
64.
Table 9, page
section.
38.
Table
(Table
SHCKO
and added note 1.
and F
51, updated values for
including F
specification in
Table
, T
46.
56.
52.
SPICCM
Table
Table 36
44), and OSERDES
to
Table 36
OUTMAX
, removed T
IN
63.
INDUTY
Table
in
/T
MAX
15.
, and T
RCKD_DI_ECC
11.
Table
Virtex-6 CXT Family Data Sheet
INMAX
MAX
Table
and
47and revised CLB switching
in
in
in
and
Table
in
Table
Table
Table 57
11, including adding note 3.
Table 37
SPICCFC
and F
RCKO_PARITY_ECC
Table
Table
36.
54. Added Note 6 to
54.
57. Updated values in
T
, T
OUTMAX
PPOUT
DSPCKO_{PCOUT,
53.
37. Updated -1 speed
(Table
. In
and added note 8.
RCKO_POINTERS
using ISE 12.2
Table
Table
/4. Updated F
.
45) switching
50. Revised
57:
: Clock CLK
MMCM
, and
MAX
51