EP2S130F1508I5 Altera, EP2S130F1508I5 Datasheet - Page 23

• Manufacturer Part Number: EP2S130F1508I5
• Description: IC STRATIX II FPGA 130K 1508FBGA
• Manufacturer: Altera
• Series: Stratix® IIr

Specifications of EP2S130F1508I5

• Number Of Logic Elements/cells: 132540
• Number Of Labs/clbs: 6627
• Total Ram Bits: 6747840
• Number Of I /o: 1126
• Voltage - Supply: 1.15 V ~ 1.25 V
• Mounting Type: Surface Mount
• Operating Temperature: -40°C ~ 100°C
• Package / Case: 1508-FBGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Number Of Gates: -

Altera Corporation
May 2007
Figure 2–11. ALM in Arithmetic Mode
While operating in arithmetic mode, the ALM can support simultaneous
use of the adder's carry output along with combinational logic outputs. In
this operation, the adder output is ignored. This usage of the adder with
the combinational logic output provides resource savings of up to 50% for
functions that can use this ability. An example of such functionality is a
conditional operation, such as the one shown in
equation for this example is:
To implement this function, the adder is used to subtract ‘Y’ from ‘X.’ If
‘X’ is less than ‘Y,’ the carry_out signal is ‘1.’ The carry_out signal is
fed to an adder where it drives out to the LAB local interconnect. It then
feeds to the LAB-wide syncload signal. When asserted, syncload
selects the syncdata input. In this case, the data ‘Y’ drives the
syncdata inputs to the registers. If ‘X’ is greater than or equal to ‘Y,’ the
syncload signal is de-asserted and ‘X’ drives the data port of the
registers.
datae0
datae1
dataf0
dataf1
datab
dataa
datad
datac
R = (X < Y) ? Y : X
4-Input
4-Input
4-Input
4-Input
LUT
LUT
LUT
LUT
carry_out
carry_in
Stratix II Device Handbook, Volume 1
adder0
adder1
D
D
reg0
reg1
Figure
Q
Q
Stratix II Architecture
2–12. The
To general or
To general or
To general or
To general or
local routing
local routing
local routing
local routing
2–15