XC4010L-5PQ208C Xilinx Inc, XC4010L-5PQ208C Datasheet - Page 10

• Manufacturer Part Number: XC4010L-5PQ208C
• Description: IC 3.3V FPGA 400 CLB'S 208-PQFP
• Manufacturer: Xilinx Inc
• Series: XC4000r

Specifications of XC4010L-5PQ208C

• Number Of Logic Elements/cells: 950
• Number Of Labs/clbs: 400
• Total Ram Bits: 12800
• Number Of I /o: 160
• Number Of Gates: 10000
• Voltage - Supply: 3 V ~ 3.6 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 208-BFQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: 122-1124

XC4000 Series Field Programmable Gate Arrays
Using Function Generators as RAM
Optional modes for each CLB make the memory look-up
tables in the F’ and G’ function generators usable as an
array of Read/Write memory cells. Available modes are
level-sensitive (similar to the XC4000/A/H families), edge-
triggered, and dual-port edge-triggered. Depending on the
selected mode, a single CLB can be configured as either a
16x2, 32x1, or 16x1 bit array.
Supported CLB memory configurations and timing modes
for single- and dual-port modes are shown in
XC4000-Series devices are the first programmable logic
devices with edge-triggered (synchronous) and dual-port
RAM accessible to the user. Edge-triggered RAM simpli-
fies system timing. Dual-port RAM doubles the effective
throughput of FIFO applications. These features can be
individually programmed in any XC4000-Series CLB.
Advantages of On-Chip and Edge-Triggered RAM
The on-chip RAM is extremely fast. The read access time
is the same as the logic delay. The write access time is
slightly slower.
any off-chip solution, because they avoid I/O delays.
Edge-triggered RAM, also called synchronous RAM, is a
feature never before available in a Field Programmable
Gate Array. The simplicity of designing with edge-triggered
RAM, and the markedly higher achievable performance,
add up to a significant improvement over existing devices
with on-chip RAM.
Three application notes are available from Xilinx that dis-
cuss edge-triggered RAM: “ XC4000E Edge-Triggered and
Dual-Port RAM Capability, ” “ Implementing FIFOs in
XC4000E RAM, ” and “ Synchronous and Asynchronous
FIFO Designs .” All three application notes apply to both
XC4000E and XC4000EX RAM.
Table 5: Supported RAM Modes
4-14
Single-Port
Dual-Port
16
x
1
Both access times are much faster than
16
x
2
32
x
1
Triggered
Timing
Edge-
Table
Sensitive
Timing
Level-
5.
RAM Configuration Options
The function generators in any CLB can be configured as
RAM arrays in the following sizes:
• Two 16x1 RAMs: two data inputs and two data outputs
• One 32x1 RAM: one data input and one data output.
One F or G function generator can be configured as a 16x1
RAM while the other function generators are used to imple-
ment any function of up to 5 inputs.
Additionally, the XC4000-Series RAM may have either of
two timing modes:
• Edge-Triggered (Synchronous): data written by the
• Level-Sensitive (Asynchronous): an external WE signal
The selected timing mode applies to both function genera-
tors within a CLB when both are configured as RAM.
The number of read ports is also programmable:
• Single Port: each function generator has a common
• Dual Port: both function generators are configured
RAM configuration options are selected by placing the
appropriate library symbol.
Choosing a RAM Configuration Mode
The appropriate choice of RAM mode for a given design
should be based on timing and resource requirements,
desired functionality, and the simplicity of the design pro-
cess. Recommended usage is shown in
The difference between level-sensitive, edge-triggered,
and dual-port RAM is only in the write operation. Read
operation and timing is identical for all modes of operation.
Table 6: RAM Mode Selection
Use for New
Designs?
Size (16x1,
Registered)
Simultaneous
Read/Write
Relative
Performance
with identical or, if preferred, different addressing for
each RAM
designated edge of the CLB clock. WE acts as a true
clock enable.
acts as the write strobe.
read and write port
together as a single 16x1 dual-port RAM with one write
port and two read ports. Simultaneous read and write
operations to the same or different addresses are
supported.
Sensitive
1/2 CLB
Level-
No
No
September 18, 1996 (Version 1.04)
X
Triggered
1/2 CLB
Edge-
Yes
No
2X
Table
Triggered
6.
Dual-Port
effective)
2X (4X
Edge-
1 CLB
Yes
Yes