XC4010L-5PQ208C Xilinx Inc, XC4010L-5PQ208C Datasheet - Page 2

• Manufacturer Part Number: XC4010L-5PQ208C
• Description: IC 3.3V FPGA 400 CLB'S 208-PQFP
• Manufacturer: Xilinx Inc
• Series: XC4000r

Specifications of XC4010L-5PQ208C

• Number Of Logic Elements/cells: 950
• Number Of Labs/clbs: 400
• Total Ram Bits: 12800
• Number Of I /o: 160
• Number Of Gates: 10000
• Voltage - Supply: 3 V ~ 3.6 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 208-BFQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: 122-1124

XC4000 Series Field Programmable Gate Arrays
Table 1: XC4000-Series Field Programmable Gate Arrays
Note: Throughout the functional descriptions in this docu-
ment, references to the XC4000E device family include the
XC4000L, and references to the XC4000EX device family
include the XC4000XL, unless explicitly stated otherwise.
References to the XC4000 Series include the XC4000E,
XC4000EX, XC4000L, and XC4000XL families. All func-
tionality in low-voltage families is the same as in the corre-
sponding 5-Volt family, except where numerical references
are made to timing, power, or current-sinking capability.
Description
XC4000-Series devices are implemented with a regular,
flexible, programmable architecture of Configurable Logic
Blocks (CLBs), interconnected by a powerful hierarchy of
versatile routing resources, and surrounded by a perimeter
of programmable Input/Output Blocks (IOBs). They have
generous routing resources to accommodate the most
complex interconnect patterns.
The devices are customized by loading configuration data
into internal memory cells. The FPGA can either actively
read its configuration data from an external serial or byte-
parallel PROM (master modes), or the configuration data
4-6
XC4028EX/XL
XC4036EX/XL
XC4044EX/XL
XC4005E/L
XC4010E/L
XC4013E/L
XC4052XL
XC4062XL
XC4003E
XC4006E
XC4008E
XC4020E
XC4025E
Device
* Max values of Typical Gate Range include 20-30% of CLBs used as RAM.
Max Logic
(No RAM)
10,000
13,000
20,000
25,000
28,000
36,000
44,000
52,000
62,000
Gates
3,000
5,000
6,000
8,000
(No Logic)
Max. RAM
10,368
12,800
18,432
25,088
32,768
32,768
41,472
51,200
61,952
73,728
3,200
6,272
8,192
Bits
(Logic and RAM)*
33,000 - 100,000
40,000 - 130,000
10,000 - 30,000
13,000 - 40,000
15,000 - 45,000
18,000 - 50,000
22,000 - 65,000
27,000 - 80,000
Larger Devices Available in the First Half of 1997
4,000 - 12,000
6,000 - 15,000
7,000 - 20,000
2,000 - 5,000
3,000 - 9,000
Gate Range
Typical
can be written into the FPGA from an external device
(slave, peripheral and Express modes).
XC4000-Series FPGAs are supported by powerful and
sophisticated software, covering every aspect of design
from schematic or behavioral entry, floorplanning, simula-
tion, automatic block placement and routing of intercon-
nects, to the creation, downloading, and readback of the
configuration bit stream.
Because Xilinx FPGAs can be reprogrammed an unlimited
number of times, they can be used in innovative designs
where hardware is changed dynamically, or where hard-
ware must be adapted to different user applications.
FPGAs are ideal for shortening design and development
cycles, and also offer a cost-effective solution for produc-
tion rates well beyond 5,000 systems per month. For lowest
high-volume unit cost, a design can first be implemented in
the XC4000E or XC4000EX, then migrated to one of Xilinx’
compatible HardWire mask-programmed devices.
Table 2
circuit functions that can be implemented in XC4000-Series
devices.
10 x 10
14 x 14
16 x 16
18 x 18
20 x 20
24 x 24
28 x 28
32 x 32
32 x 32
36 x 36
40 x 40
44 x 44
48 x 48
Matrix
CLB
shows density and performance for a few common
Blocks
Logic
1,024
1,024
1,296
1,600
1,936
2,304
Total
100
196
256
324
400
576
784
Flip-Flops
September 18, 1996 (Version 1.04)
Number
1,120
1,536
2,016
2,560
2,560
3,168
3,840
4,576
5,376
360
616
768
936
of
per side
Decode
Inputs
Max.
108
120
132
144
30
42
48
54
60
72
84
96
96
User I/O
Max.
112
128
144
160
192
224
256
256
288
320
352
384
80