XC4010L-5PQ208C Xilinx Inc, XC4010L-5PQ208C Datasheet - Page 66

• Manufacturer Part Number: XC4010L-5PQ208C
• Description: IC 3.3V FPGA 400 CLB'S 208-PQFP
• Manufacturer: Xilinx Inc
• Series: XC4000r

Specifications of XC4010L-5PQ208C

• Number Of Logic Elements/cells: 950
• Number Of Labs/clbs: 400
• Total Ram Bits: 12800
• Number Of I /o: 160
• Number Of Gates: 10000
• Voltage - Supply: 3 V ~ 3.6 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 208-BFQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: 122-1124

XC4000 Series Field Programmable Gate Arrays
Master Parallel Modes
In the two Master Parallel modes, the lead FPGA directly
addresses an industry-standard byte-wide EPROM, and
accepts eight data bits just before incrementing or decre-
menting the address outputs.
The eight data bits are serialized in the lead FPGA, which
then presents the preamble data—and all data that over-
flows the lead device—on its DOUT pin. There is an inter-
nal delay of 1.5 CCLK periods, after the rising CCLK edge
that accepts a byte of data (and also changes the EPROM
address) until the falling CCLK edge that makes the LSB
(D0) of this byte appear at DOUT. This means that DOUT
changes on the falling CCLK edge, and the next FPGA in
the daisy chain accepts data on the subsequent rising
CCLK edge.
4-70
Figure 57: Master Parallel Mode Circuit Diagram
PROGRAM
NOTE:M0 can be shorted
to Ground if not used
as I/O.
4.7K
VCC
4.7K
DATA BUS
DOUT
INIT
PROGRAM
D7
D6
D5
D4
D3
D2
D1
D0
M0
HIGH
LOW
M1
or
N/C
M2
DONE
CCLK
A16
A17
A15
A14
A13
A12
A11
A10
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0
8
. . .
. . .
. . .
. . .
. . .
OE
CE
A12
A11
A10
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0
TO DIN OF OPTIONAL
DAISY-CHAINED FPGAS
TO CCLK OF OPTIONAL
DAISY-CHAINED FPGAS
(OR LARGER)
EPROM
(8K x 8)
D7
D6
D5
D4
D3
D2
D1
D0
USER CONTROL OF HIGHER
ORDER PROM ADDRESS BITS
CAN BE USED TO SELECT BETWEEN
ALTERNATIVE CONFIGURATIONS
The PROM address pins can be incremented or decre-
mented, depending on the mode pin settings. This option
allows the FPGA to share the PROM with a wide variety of
microprocessors and microcontrollers. Some processors
must boot from the bottom of memory (all zeros) while oth-
ers must boot from the top. The FPGA is flexible and can
load its configuration bitstream from either end of the mem-
ory.
Master Parallel Up mode is selected by a <100> on the
mode pins (M2, M1, M0). The EPROM addresses start at
00000 and increment.
Master Parallel Down mode is selected by a <110> on the
mode pins. The EPROM addresses start at 3FFFF and
decrement.
DONE
DIN
CCLK
PROGRAM
M0
XC4000E/EX
September 18, 1996 (Version 1.04)
SLAVE
N/C
M1
M2
DOUT
INIT
X6697