XC4010L-5PQ208C Xilinx Inc, XC4010L-5PQ208C Datasheet - Page 71

• Manufacturer Part Number: XC4010L-5PQ208C
• Description: IC 3.3V FPGA 400 CLB'S 208-PQFP
• Manufacturer: Xilinx Inc
• Series: XC4000r

Specifications of XC4010L-5PQ208C

• Number Of Logic Elements/cells: 950
• Number Of Labs/clbs: 400
• Total Ram Bits: 12800
• Number Of I /o: 160
• Number Of Gates: 10000
• Voltage - Supply: 3 V ~ 3.6 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 208-BFQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: 122-1124

Notes: 1. Configuration must be delayed until the INIT pins of all daisy-chained FPGAs are High.
This timing diagram shows very relaxed requirements. Data need not be held beyond the rising edge of
go active within 60 ns after the end of
may not be terminated until RDY/
Figure 62: Asynchronous Peripheral Mode Programming Switching Characteristics
September 18, 1996 (Version 1.04)
RDY/BUSY
RS, CS1
WS/CS0
Write
RDY
D0-D7
DOUT
CCLK
2. The time from the end of WS to CCLK cycle for the new byte of data depends on the completion of previous byte processing
3. CCLK and DOUT timing is tested in slave mode.
4. T
and the phase of the internal timing generator for CCLK.
occurs when a byte is loaded into an empty parallel-to-serial converter. The longest T
loaded into the input register before the second-level buffer has started shifting out data.
BUSY
Effective Write time
(CS0, WS=Low; RS, CS1=High)
DIN setup time
DIN hold time
RDY/BUSY delay after end of
Write or Read
RDY/BUSY active after beginning
of Read
RDY/BUSY Low output (Note 4)
indicates that the double-buffered parallel-to-serial converter is not yet ready to receive new data. The shortest T
Write to LCA
Description
1 T
T
CA
WTRB
2 T
BUSY
DC
4
WS
has been High for one CCLK period.
Previous Byte D6
. A new write may be asserted immediately after RDY/
3 T
CD
1
2
3
4
7
6
Symbol
6 T
T
T
BUSY
T
T
T
WTRB
BUSY
CA
DC
CD
D7
Min
100
60
0
2
7
BUSY
D0
Read Status
occurs when a new word is
READY
BUSY
Max
60
60
9
D1
BUSY
4
goes Low, but write
WS
D2
. RDY/
periods
CCLK
Units
ns
ns
ns
ns
ns
BUSY
BUSY
RS, CS0
WS, CS1
D7
X6097
4-75
will