MPC8541EVTAJD Freescale Semiconductor, MPC8541EVTAJD Datasheet
MPC8541EVTAJD
Specifications of MPC8541EVTAJD
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MPC8541EVTAJD Summary of contents
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... PowerQUICC™ III Integrated Communications Processor Reference Manual. To locate any published errata or updates for this document refer to http://www.freescale.com or contact your Freescale sales office. © Freescale Semiconductor, Inc., 2008. All rights reserved. MPC8541EEC Rev. 4.2, 1/2008 Contents 1. Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 2. Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . 7 3 ...
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... Controller Figure 1. MPC8541E Block Diagram Figure 1 shows the 256 Kbyte L2 Cache/ SRAM e500 Core 32-Kbyte L1 32-Kbyte L1 I Cache D Cache Core Complex Bus 64/32b PCI Controller 0/32b PCI Controller DMA Controller 10/100/1000 MAC MII, GMII, TBI, RTBI, RGMIIs 10/100/1000 MAC Freescale Semiconductor ...
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... Can act as a 256-Kbyte or two 128-Kbyte memory-mapped SRAM arrays — Can be partitioned into 128-Kbyte L2 cache plus 128-Kbyte SRAM — Full ECC support on 64-bit boundary in both cache and SRAM modes MPC8541E PowerQUICC™ III Integrated Communications Processor Hardware Specification, Rev. 4.2 Freescale Semiconductor Overview 3 ...
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... Supports 16 programmable interrupt and processor task priority levels — Supports 12 discrete external interrupts — Supports 4 message interrupts with 32-bit messages — Supports connection of an external interrupt controller such as the 8259 programmable interrupt controller MPC8541E PowerQUICC™ III Integrated Communications Processor Hardware Specification, Rev. 4.2 4 Freescale Semiconductor ...
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... Support for Ethernet physical interfaces: – 10/100/1000 Mbps IEEE 802.3 GMII – 10/100 Mbps IEEE 802.3 MII – 10 Mbps IEEE 802.3 MII MPC8541E PowerQUICC™ III Integrated Communications Processor Hardware Specification, Rev. 4.2 Freescale Semiconductor 2 C addressing mode Overview 2 C interface ...
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... Supports PCI-to-memory and memory-to-PCI streaming — Memory prefetching of PCI read accesses — Supports posting of processor-to-PCI and PCI-to-memory writes — PCI 3.3-V compatible MPC8541E PowerQUICC™ III Integrated Communications Processor Hardware Specification, Rev. 4.2 6 Freescale Semiconductor ...
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... I/O cell, but are included for a more complete reference. These are not purely I/O buffer design specifications. 2.1 Overall DC Electrical Characteristics This section covers the ratings, conditions, and other characteristics. MPC8541E PowerQUICC™ III Integrated Communications Processor Hardware Specification, Rev. 4.2 Freescale Semiconductor Electrical Characteristics 7 ...
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... Unit –0.3 to 1.32 V 0.3 to 1.43 (for 1 GHz only) –0.3 to 1.32 V 0.3 to 1.43 (for 1 GHz only) –0.3 to 3.63 V –0.3 to 3.63 V –0.3 to 2.75 –0.3 to 3.63 V –0.3 to ( –0.3 to ( –0.3 to ( –0.3 to (OV + 0.3 –0.3 to ( –55 to 150 °C Figure 2. Freescale Semiconductor Notes ...
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... DDR DRAM reference Three-speed Ethernet signals PCI, local bus, DUART, SYSCLK, system control and power management, I JTAG signals Die-junction Temperature MPC8541E PowerQUICC™ III Integrated Communications Processor Hardware Specification, Rev. 4.2 Freescale Semiconductor NOTE NOTE Symbol Recommended Value V 1.2 V ± 1.3 V± (for 1 GHz only) AV 1.2 V ± ...
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... MPC8541E PowerQUICC™ III Integrated Communications Processor Hardware Specification, Rev GND Not to Exceed 10 SYS refers to the clock period associated with the SYSCLK signal. Table and /OV / Table 2 for actual 2. The input voltage threshold scales with based receivers are simple CMOS I/O signal (nominally set to REF Freescale Semiconductor ...
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... The drive strength of the local bus interface is determined by the configuration of the appropriate bits in PORIMPSCR. 2. The drive strength of the PCI interface is determined by the setting of the PCI_GNT1 signal at reset. MPC8541E PowerQUICC™ III Integrated Communications Processor Hardware Specification, Rev. 4.2 Freescale Semiconductor 11 ns (Min) +7 ...
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... T DD Table (3)(4) (5) (W) Maximum Power 4.4 6.1 4.7 6.5 5.0 6.8 4.9 6.7 5.4 7.2 5.8 8.6 5.5 7.4 6.0 8.8 9.0 12.2 = 105° C, and a j target, and I 105° C, and j Freescale Semiconductor 4. (W) ...
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... MHz 32b, 83 MHz 32b, 66 MHz 32b, 33 MHz TSEC I/O MII GMII or TBI RGMII or RTBI CPM - FCC MII RMII HDLC 16 Mbps MPC8541E PowerQUICC™ III Integrated Communications Processor Hardware Specification, Rev. 4.2 Freescale Semiconductor Table 5. Typical I/O Power Dissipation (2.5 V) (3 ...
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... G125R t — G125F t /t G125H G125 GMII, TBI 45 47 Typical Max Unit Notes — 166 MHz — — ns 1.0 1.2 ns — — +/- 150 ps Typical Max Unit Notes 125 — MHz 8 — ns — 1.0 ns — 1.0 ns — Freescale Semiconductor 1 — — — ...
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... DLL lock times are a function of the ratio between the output clock and the platform (or CCB) clock. A 2:1 ratio results in the minimum and an 8:1 ratio results in the maximum. 2. The CCB clock is determined by the SYSCLK × platform PLL ratio. MPC8541E PowerQUICC™ III Integrated Communications Processor Hardware Specification, Rev. 4.2 Freescale Semiconductor Table 8. RTC AC Timing Specifications Symbol Min ...
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... DIO = 2.5 V ± 0.125 MHz 25° Max Unit 2.625 V 0.51 × – 0. 0.04 V REF + 0. 0 – 0.18 V REF μA 10 — mA — mA μ Min Max Unit — 0 /2, V (peak to peak) = 0.2 V. OUT DD OUT Freescale Semiconductor Notes — — 4 — — — Notes 1 1 ...
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... Skew between any MCK to ADDR/CMD ADDR/CMD output setup with respect to MCK ADDR/CMD output hold with respect to MCK MCS(n) output setup with respect to MCK MPC8541E PowerQUICC™ III Integrated Communications Processor Hardware Specification, Rev. 4.2 Freescale Semiconductor of 2.5 V ± 5%. DD Symbol Min V — ...
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... AOSKEW Max Unit — 0.3 0.5 0.6 — ps — ps –0.5 × t – 0.9 +0.3 ns MCK 0.3 ns memory clock MCK describes the DDR timing DDKHMH follows the symbol DDKHMP Freescale Semiconductor Notes for ...
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... DDR SDRAM output timing diagram for the source synchronous mode. MCK[n] MCK[n] ADDR/CMD Write A0 t DDKHMP MDQS[n] MDQ[x] Figure 5. DDR SDRAM Output Timing Diagram for Source Synchronous Mode MPC8541E PowerQUICC™ III Integrated Communications Processor Hardware Specification, Rev. 4.2 Freescale Semiconductor MCK[n] MCK[n] t MCK t AOSKEWmax) CMD t AOSKEW(min) CMD ...
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... GV DD Symbol Test Condition ≥ (min OUT OH ≤ (max) IL OUT min –100 μ 100 μ min symbol referenced Ω L Notes Min Max 0.3 DD –0.3 0.8 — ±5 OV – 0.2 — DD — 0.2 Table 1 and Table 2. Freescale Semiconductor Unit V V μ ...
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... GMII driver and receiver supply potentials is implicit in these specifications. The RGMII and RTBI signals are based on a 2.5-V CMOS interface voltage as defined by JEDEC EIA/JESD8-5. MPC8541E PowerQUICC™ III Integrated Communications Processor Hardware Specification, Rev. 4.2 Freescale Semiconductor Table 17. DUART AC Timing Specifications Value ...
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... GND – –0 –15 IL symbol referenced in IN Min Max 3.13 3.47 2. 0.3 DD GND 0.50 1. 0.3 DD –0.3 0.90 — 40 –600 — and Table 2. Max 2. 0 0.3 DD 0.70 — 10 — Table 1and Table 2. Freescale Semiconductor Unit μA μA Unit μA μA ...
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... Signal timings are measured at 0.7 V and 1.9 V voltage levels. 3. Guaranteed by characterization. 4. Guaranteed by design. Figure 7 shows the GMII transmit AC timing diagram. GTX_CLK TXD[7:0] TX_EN TX_ER MPC8541E PowerQUICC™ III Integrated Communications Processor Hardware Specification, Rev. 4.2 Freescale Semiconductor of 3.3 V ± 5 Symbol t GTX t /t GTXH ...
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... Figure 9. GMII Receive AC Timing Diagram Min Typ Max — 8.0 — 40 — 60 2.0 — — 0.5 — — — — 1.0 for outputs. For example, t GRDVKH symbolizes GMII receive timing (GR) GRDXKL clock reference (K) going to the low (L) GRX Ω GRXR Freescale Semiconductor Unit ...
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... Signal timings are measured at 0.7 V and 1.9 V voltage levels. 3. Guaranteed by design. Figure 10 shows the MII transmit AC timing diagram. TX_CLK TXD[3:0] TX_EN TX_ER MPC8541E PowerQUICC™ III Integrated Communications Processor Hardware Specification, Rev. 4.2 Freescale Semiconductor of 3.3 V ± 5 Symbol 2 t MTX t MTX ...
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... MRX t t MRXH MRXF Valid Data t MRDVKH Figure 11. MII Receive AC Timing Diagram Min Typ Max — 400 — — 40 — 35 — 65 10.0 — — 10.0 — — 1.0 — 4.0 symbolizes MII MRDVKH clock reference MRX t MRXR t MRDXKH Freescale Semiconductor Unit ...
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... R (rise (fall). 2. Signal timings are measured at 0.7 V and 1.9 V voltage levels. 3. Guaranteed by design. Figure 12 shows the TBI transmit AC timing diagram. GTX_CLK TCG[9:0] MPC8541E PowerQUICC™ III Integrated Communications Processor Hardware Specification, Rev. 4.2 Freescale Semiconductor of 3.3 V ± 5 Symbol t TTX t ...
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... Max 16.0 7.5 — 8.5 40 — 60 2.5 — — 1.5 — — 0.7 — 2.4 for outputs. For example, t symbolizes TBI receive timing (TR) with TRDXKH clock reference (K) going to the high (H) state. t TRXR Valid Data t TRDXKH t TRDXKH t TRDVKH Freescale Semiconductor Unit TRDVKH ...
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... Guaranteed by characterization. 6. Guaranteed by design. 7. Signal timings are measured at 0.5 and 2.0 V voltage levels. MPC8541E PowerQUICC™ III Integrated Communications Processor Hardware Specification, Rev. 4.2 Freescale Semiconductor Specifications of 2.5 V ± 5 Symbol ...
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... TXERR RXD[8:5] RXD[3:0] RXD[7:4] t SKRGT RXD[4] RXD[9] RXDV RXERR Section 8.1, “Three-Speed Ethernet Controller (TSEC) Table 27. Conditions — –1 Min 1 Min — IH — RGT t RGTH t SKRGT t SKRGT Min Max 3.13 3.47 2. 0.3 DD GND 0.50 1.70 — — 0.90 Freescale Semiconductor Unit ...
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... This parameter is dependent on the CCB clock speed (that is, for a CCB clock of 267 MHz, the delay and for a CCB clock of 333 MHz, the delay is 48 ns). 4. Guaranteed by design. MPC8541E PowerQUICC™ III Integrated Communications Processor Hardware Specification, Rev. 4.2 Freescale Semiconductor Conditions 1 LV ...
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... MDC t t MDCF MDCH t MDDVKH t MDDXKH t MDKHDX Test Condition ≥ (min OUT OH ≤ (max) IL OUT min –2mA min 2mA symbol referenced MDCR Min Max 0.3 DD –0.3 0.8 — ±5 OV –0.2 — DD — 0.2 Table 1 and Table 2. Freescale Semiconductor Unit V V μ ...
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... Output hold from local bus clock (except LAD/LDP and LALE) Output hold from local bus clock for LAD/LDP Local bus clock to output high Impedance (except LAD/LDP and LALE) MPC8541E PowerQUICC™ III Integrated Communications Processor Hardware Specification, Rev. 4.2 Freescale Semiconductor 7 1 Configuration Symbol t LBK ...
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... For example, t LBIXKH1 clock reference (K) goes LBK clock reference ( LBK of the signal Min Max Unit 6.0 — ns 1.8 3.4 ns — 150 ps 5.2 — ns 5.1 — ns –1.3 — ns –0.8 — ns 1.5 — ns — 0.5 ns 2.0 — 0.7 ns 2.2 Freescale Semiconductor Notes 5, 9 Notes ...
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... Maximum possible clock skew between a clock LCLK[m] and a relative clock LCLK[n]. Skew measured between complementary signals Guaranteed by characterization. 9. Guaranteed by design. Figure 16 provides the AC test load for the local bus. Output MPC8541E PowerQUICC™ III Integrated Communications Processor Hardware Specification, Rev. 4.2 Freescale Semiconductor 7 Configuration Symbol LWE[0: LBKLOV3 LWE[0: (default) LWE[0: ...
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... Output (Address) Signal: LAD[0:31] LALE Figure 17. Local Bus Signals, Nonspecial Signals Only (DLL Enabled) MPC8541E PowerQUICC™ III Integrated Communications Processor Hardware Specification, Rev. 4 LBIVKH1 t LBIVKH1 t LBKHOZ1 t t LBKHOV1 LBKHOX1 t LBKHOZ2 t t LBKHOV2 LBKHOX2 t LBKHOZ2 t t LBKHOX2 LBKHOV3 t LBOTOT t LBIXKH1 t LBIXKH1 Freescale Semiconductor ...
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... LA[27:31]/LBCTL/LBCKE/LOE/ LSDA10/LSDWE/LSDRAS/ LSDCAS/LSDDQM[0:3] Output (Data) Signals: LAD[0:31]/LDP[0:3] Output (Address) Signal: LAD[0:31] LALE Figure 18. Local Bus Signals, Nonspecial Signals Only (DLL Bypass Mode) MPC8541E PowerQUICC™ III Integrated Communications Processor Hardware Specification, Rev. 4.2 Freescale Semiconductor t LBKHKT t LBIVKH1 t LBIVKH2 t LBKLOV1 t ...
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... Input Signals: LAD[0:31]/LDP[0:3] UPM Mode Output Signals: LCS[0:7]/LBS[0:3]/LGPL[0:5] Figure 19. Local Bus Signals, GPCM/UPM Signals for LCCR[CLKDIV (DLL Enabled) MPC8541E PowerQUICC™ III Integrated Communications Processor Hardware Specification, Rev. 4 LBKHOZ1 t LBKHOV1 t LBIVKH2 t LBIVKH1 t LBKHOZ1 t LBKHOV1 t LBIXKH2 t LBIXKH1 Freescale Semiconductor ...
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... Input Signals: LAD[0:31]/LDP[0:3] (DLL Bypass Mode) UPM Mode Output Signals: LCS[0:7]/LBS[0:3]/LGPL[0:5] Figure 20. Local Bus Signals, GPCM/UPM Signals for LCCR[CLKDIV (DLL Bypass Mode) MPC8541E PowerQUICC™ III Integrated Communications Processor Hardware Specification, Rev. 4.2 Freescale Semiconductor t LBKHKT t t LBKLOX1 LBKLOV1 ...
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... Input Signals: LAD[0:31]/LDP[0:3] UPM Mode Output Signals: LCS[0:7]/LBS[0:3]/LGPL[0:5] Figure 21. Local Bus Signals, GPCM/UPM Signals for LCCR[CLKDIV (DLL Enabled) MPC8541E PowerQUICC™ III Integrated Communications Processor Hardware Specification, Rev. 4 LBKHOZ1 t LBKHOV1 t LBIVKH2 t LBIVKH1 t LBKHOZ1 t LBKHOV1 t LBIXKH2 t LBIXKH1 Freescale Semiconductor ...
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... Input Signals: LAD[0:31]/LDP[0:3] (DLL Bypass Mode) UPM Mode Output Signals: LCS[0:7]/LBS[0:3]/LGPL[0:5] Figure 22. Local Bus Signals, GPCM/UPM Signals for LCCR[CLKDIV (DLL Bypass Mode) MPC8541E PowerQUICC™ III Integrated Communications Processor Hardware Specification, Rev. 4.2 Freescale Semiconductor t LBKHKT t t LBKLOX1 LBKLOV1 ...
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... Table 32. CPM DC Electrical Characteristics Symbol Condition –8 8 –2 3 NOTE: Rise/Fall Time on CPM Input Pins Min Max Unit Notes 2.0 3.465 V 1 GND 0 2.4 — — 0 2.4 — — 0 Symbol Min Unit FIIVKH FIIXKH t 2.5 ns FEIVKH FEIXKH NIIVKH NIIXKH NEIVKH NEIXKH PIIVKH Freescale Semiconductor ...
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... AC test load for the CPM. Output MPC8541E PowerQUICC™ III Integrated Communications Processor Hardware Specification, Rev. 4.2 Freescale Semiconductor (first two letters of functional block)(signal)(state) (K) going to the high (H) state or setup time. (first two letters of functional block)(signal)(state) (reference)(state) for outputs ...
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... Ethernet collision timing on FCCs. COL (Input) Figure 26. Ethernet Collision AC Timing Diagram (FCC) MPC8541E PowerQUICC™ III Integrated Communications Processor Hardware Specification, Rev. 4.2 44 Table 33 and t FIIXKH t FIIVKH t FIKHOX t FIKHOX t FEIXKH t FEIVKH t FEKHOX t FEKHOX t FCCH Table 34. Note that although the Freescale Semiconductor ...
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... SPI AC timings are internal mode when it is master because SPICLK is an output, and external mode when it is slave. 2 SPI AC timings refer always to SPICLK Sys clk t PIO inputs PIO outputs MPC8541E PowerQUICC™ III Integrated Communications Processor Hardware Specification, Rev. 4.2 Freescale Semiconductor t NEIXKH t NEKHOX t NIIXKH t NIIVKH ...
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... SCL t SCHCL t SCLDX t t SRISE SFALL Figure 30. CPM I2C Bus Timing Diagram All Frequencies Max (1) F MAX BRGCLK/48 ) — SCL ) — SCL ) — SCL (2) ) SCL ) — SCL ) — SCL ) — SCL 1/( SCL 1/( SCL ) — SCL t SDVCH t SCHDH Freescale Semiconductor Unit ...
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... Start condition hold time Data hold time Data setup time SDA/SCL rise time SDA/SCL fall time Stop condition setup time MPC8541E PowerQUICC™ III Integrated Communications Processor Hardware Specification, Rev. 4.2 Freescale Semiconductor Table 36. CPM I2C Timing (f =100 kHz) SCL Expression f SCL ...
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... Figure 35. 1 Min Max Unit Notes 0 33.3 MHz 30 — — — — 0 — — 25 — — — — — the midpoint of the signal in TCLK for outputs. For example, t JTDVKH symbolizes JTAG timing (JT) with respect to Freescale Semiconductor — — — — ...
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... JTAG External Clock Boundary Data Inputs t JTKLDX Boundary Data Outputs Boundary Output Data Valid Data Outputs MPC8541E PowerQUICC™ III Integrated Communications Processor Hardware Specification, Rev. 4.2 Freescale Semiconductor = 50 Ω JTKHKL t JTG VM = Midpoint Voltage (OV DD /2) VM ...
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... V ± 5%. DD Symbol 0.7 × 0.1 × I2KLKV t I2KHKL switched off JTIXKH Input Data Valid Output Data Valid 2 C interface of the MPC8541E. Min Max Unit 0.3 × OV –0 0.2 × 250 μA –10 10 — Freescale Semiconductor Notes — — — ...
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... LOW period (t I2DVKH capacitance of one bus line in pF Guaranteed by design. MPC8541E PowerQUICC™ III Integrated Communications Processor Hardware Specification, Rev. 4.2 Freescale Semiconductor 2 C interface of the MPC8541E. 2 Table 40 Electrical Specifications Table 39) ...
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... Test Condition ≥ (min OUT OH ≤ (max) IL OUT min –100 μ min 100 μ symbol referenced Ω I2KHKL I2CF t I2CR t I2PVKH P 1 Min Max 0.3 DD –0.3 0.8 — ±5 OV – 0.2 — DD — 0.2 Table 1 and Table 2. Freescale Semiconductor S Unit V V μ ...
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... The reset assertion timing requirement for HRESET is 100 μs. 9. Guaranteed by characterization. 10.Guaranteed by design. Figure 16 provides the AC test load for PCI. Output MPC8541E PowerQUICC™ III Integrated Communications Processor Hardware Specification, Rev. 4.2 Freescale Semiconductor Table 42 provides the PCI AC timing specifications at 66 NOTE NOTE 1 Symbol ...
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... Pitch Minimum module height 3.07 mm Maximum module height 3.75 mm Solder Balls Ball diameter (typical) MPC8541E PowerQUICC™ III Integrated Communications Processor Hardware Specification, Rev. 4 PCIVKH CLK t PCKHOV t PCKHOZ Output 8.7 mm × 9.3 mm × 0. × 783 Sn/36 Pb PCIXKH Freescale Semiconductor ...
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... Capacitors may not be present on all devices. 6. Caution must be taken not to short capacitors or exposed metal capacitor pads on package top. 7. The socket lid must always be oriented to A1. MPC8541E PowerQUICC™ III Integrated Communications Processor Hardware Specification, Rev. 4.2 Freescale Semiconductor Package and Pin Listings 55 ...
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... AF5 AF3, AE4, AG4, AE5 AE6 AG5, AH5, AF6, AG6 AH25 AH27 AC18 Power Pin Type Notes Supply I/O OV — DD I/O OV — — I/O OV — — DD I/O OV — — — DD I/O OV — DD Freescale Semiconductor ...
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... MWE MRAS MCAS MCS[0:3] MCKE[0:1] MCK[0:5] MCK[0:5] MSYNC_IN MSYNC_OUT LA[27] MPC8541E PowerQUICC™ III Integrated Communications Processor Hardware Specification, Rev. 4.2 Freescale Semiconductor Package Pin Number AD18, AE18, AE19, AD19 AC22 AD20 AC20 AD21 AE21, AD22, AE22, AC23 AE20 AC21 AC19 ...
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... V28 V27 V23 V22 T27 T28 AB28, AB27 T23, P24 DMA H5, G4 H6, G5 H7, G6 Programmable Interrupt Controller AG17 AG16 Power Pin Type Notes Supply I/O OV — — — — I/O OV — I — — — — — — — DD Freescale Semiconductor ...
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... TSEC1_RX_ER TSEC1_RX_CLK Three-Speed Ethernet Controller (Gigabit Ethernet 2) TSEC2_TXD[7:4] TSEC2_TXD[3:0] TSEC2_TX_EN TSEC2_TX_ER TSEC2_TX_CLK TSEC2_GTX_CLK MPC8541E PowerQUICC™ III Integrated Communications Processor Hardware Specification, Rev. 4.2 Freescale Semiconductor Package Pin Number AB20 Y20 AF26 AH24 AB21 Ethernet Management Interface F1 E1 Gigabit Reference Clock ...
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... AH23 System Control AH16 AG20 AF20 M11 G1 Debug N12 G2 J9 Clock AH21 AB23 AF22 Power Pin Type Notes Supply I LV — — — — — — — — — — — — — — — — — DD Freescale Semiconductor ...
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... THERM0 THERM1 ASLEEP MPC8541E PowerQUICC™ III Integrated Communications Processor Hardware Specification, Rev. 4.2 Freescale Semiconductor Package Pin Number JTAG AF21 AG21 AF19 AF23 AG23 DFT AG19 AB22 AG22 AH20 AG26 Thermal Management AG2 AH3 Power Management AG18 Power and Ground Signals ...
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... Reference LV — DD Voltage; Three-Speed Ethernet I/O (2.5 V, 3.3 V) Reference MV — REF Voltage Signal; DDR — — 16 PCI, 10/100 OV — DD Ethernet, and other Standard (3.3 V) — — 15 Power for Core (1.2 V) — — 13 Power for Core V — DD (1.2 V) I/0 OV — DD Freescale Semiconductor ...
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... If this signal is used as both an input and an output, a weak pull-up (~10kΩ) is required on this pin. 22. MSYNC_IN and MSYNC_OUT should be connected together for proper operation. MPC8541E PowerQUICC™ III Integrated Communications Processor Hardware Specification, Rev. 4.2 Freescale Semiconductor Package Pin Number R7 W6, W7, W8 AC3, AC2, AC1, AD6, AE3, AE2 Ratio.” ...
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... MHz Min 100 Ratio,” for ratio settings. Table 44 provides the clocking 833 MHz 1000 MHz Unit Notes Max Min Max 833 400 1000 MHz Ratio,” for ratio settings. Unit Notes Max 166 MHz Section 15.2, “Platform/System PLL Freescale Semiconductor ...
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... There is no default for this PLL ratio; these signals must be pulled to the desired values. For specifications on the PCI_CLK, refer to the PCI 2.2 Specification. Binary Value of LA[28:31] Signals MPC8541E PowerQUICC™ III Integrated Communications Processor Hardware Specification, Rev. 4.2 Freescale Semiconductor Table 46. Table 46. CCB Clock Ratio Ratio Description ...
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... SYSCLK (MHz Platform/CCB Frequency (MHz) 200 267 208 333 200 250 200 267 333 225 300 250 333 300 Table 47. 83 100 111 133 200 222 267 250 300 333 333 Freescale Semiconductor ...
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... This spring force should not exceed 10 pounds force. MPC8541E PowerQUICC™ III Integrated Communications Processor Hardware Specification, Rev. 4.2 Freescale Semiconductor Table 49. Package Thermal Characteristics Figure 42. The heat sink should be attached to the printed-circuit ...
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... Harrisburg, PA 17105-3668 Internet: www.chipcoolers.com Wakefield Engineering 33 Bridge St. Pelham, NH 03076 Internet: www.wakefield.com MPC8541E PowerQUICC™ III Integrated Communications Processor Hardware Specification, Rev. 4.2 68 FC-PBGA Package Heat Sink Heat Sink Clip Lid Die Printed-Circuit Board 603-224-9988 408-749-7601 818-842-7277 408-436-8770 800-522-6752 603-635-5102 Freescale Semiconductor ...
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... Substrate and Solder Balls (25 × 25 × 1.6 mm MPC8541E PowerQUICC™ III Integrated Communications Processor Hardware Specification, Rev. 4.2 Freescale Semiconductor Unit W/(m × K) 360 360 z 360 Side View of Model (Not to Scale) x 4.4 1.2 y Top View of Model (Not to Scale) Figure 43 ...
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... If the support fixture around the package prevents sliding off the heat sink, MPC8541E PowerQUICC™ III Integrated Communications Processor Hardware Specification, Rev. 4.2 70 Table 49, the intrinsic internal conduction thermal resistance paths Radiation Convection Heat Sink Thermal Interface Material Die/Package Die Junction Package/Leads Radiation Convection Freescale Semiconductor ...
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... Shin-Etsu MicroSi, Inc. 10028 S. 51st St. Phoenix, AZ 85044 Internet: www.microsi.com The Bergquist Company th 18930 West 78 St. MPC8541E PowerQUICC™ III Integrated Communications Processor Hardware Specification, Rev. 4.2 Freescale Semiconductor Silicone Sheet (0.006 in.) Bare Joint Floroether Oil Sheet (0.007 in.) Graphite/Oil Sheet (0.005 in.) Synthetic Grease ...
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... INT JC is obtained 30°C + 5°C + (0.96°C/W + θ versus airflow velocity for a Thermalloy heat sink SA of about 3.3°C/W, thus SA+ Table 5. ) may be in the range of 5° may be about 1°C/W. For the INT = 0.96, and a power consumption (P ) × 8 Freescale Semiconductor ) ...
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... For applications with significant vibration requirements, silicone damping material can be applied between the heat sink and plastic frame. MPC8541E PowerQUICC™ III Integrated Communications Processor Hardware Specification, Rev. 4.2 Freescale Semiconductor Thermalloy #2328B Pin-fin Heat Sink (25 × 28 × 15 mm) 0 ...
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... Figure 47 and provide exploded views of the plastic fence, heat sink, and spring clip. Figure 47. Exploded Views ( Heat Sink Attachment using a Plastic Fence MPC8541E PowerQUICC™ III Integrated Communications Processor Hardware Specification, Rev. 4.2 74 Freescale Semiconductor ...
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... For these reasons, we recommend using conjugate heat transfer models for the boards, as well as, system-level designs. MPC8541E PowerQUICC™ III Integrated Communications Processor Hardware Specification, Rev. 4.2 Freescale Semiconductor Thermal 75 ...
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... The ) DD Section 15.3, “e500 Core PLL 5 respectively). The AV level should always be equivalent through a low frequency filter scheme such DD Figure 49, one to each of the five AV Ratio.” Ratio.” DD pins pin being supplied to minimize DD Freescale Semiconductor ...
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... GND. Then, the value of each resistor is varied until the pad voltage is OV output impedance is the average of two components, the resistances of the pull-up and pull-down devices. MPC8541E PowerQUICC™ III Integrated Communications Processor Hardware Specification, Rev. 4.2 Freescale Semiconductor 10 Ω 2.2 µF 2.2 µ ...
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... Table 50. Impedance Characteristics Management 43 Target 43 Target NA Table 105°C. j and R are designed to be close to each SW2 SW1 . Second, the output voltage is measured . The term source PCI DDR DRAM Symbol Unit 25 Target 20 Target 25 Target 20 Target Freescale Semiconductor = R term , DD Ω Ω Ω DIFF ...
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... TCK and TMS signals, generally systems assert TRST during the power-on reset flow. Simply tying TRST to HRESET is not practical because the JTAG interface is also used for accessing the common on-chip processor (COP) function. MPC8541E PowerQUICC™ III Integrated Communications Processor Hardware Specification, Rev. 4.2 Freescale Semiconductor System Design Information 79 ...
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... MPC8541E PowerQUICC™ III Integrated Communications Processor Hardware Specification, Rev. 4.2 80 allows the COP port to independently assert HRESET or TRST, Figure 51, for connection to the target system, and is 2 COP_TDO COP_TDI 3 4 COP_TRST COP_VDD_SENSE COP_TCK 7 8 COP_CHKSTP_IN COP_TMS KEY 13 No pin GND 15 16 Figure 51. COP Connector Physical Pinout Figure 51 is common to Freescale Semiconductor ...
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... Tie TCK to OV through a 10 kΩ resistor. This prevents TCK from changing state and reading DD incorrect data into the device. • No connection is required for TDI, TMS, or TDO. MPC8541E PowerQUICC™ III Integrated Communications Processor Hardware Specification, Rev. 4.2 Freescale Semiconductor System Design Information 81 ...
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... COP_TRST 10 Ω 2 COP_VDD_SENSE NC COP_CHKSTP_OUT 10 kΩ COP_CHKSTP_IN COP_TMS COP_TDO COP_TDI COP_TCK 10 kΩ Figure 52. JTAG Interface Connection kΩ 6 SRESET 1 10 kΩ HRESET 10 kΩ 10 kΩ 10 kΩ 10 kΩ 1 TRST CKSTP_OUT 10 kΩ CKSTP_IN TMS TDO TDI TCK Freescale Semiconductor ...
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... Corrected symbols for body rows 9–15, effectively changing them from a high state to a low state. 0 6/2005 Initial Release. MPC8541E PowerQUICC™ III Integrated Communications Processor Hardware Specification, Rev. 4.2 Freescale Semiconductor Table 51. Document Revision History Substantive Change(s) Figure 3, ““Maximum AC Waveforms on PCI interface for 3.3-V Signaling.” Section 2.1.2, “Power Sequencing.” ...
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... Table 52. Part Numbering Nomenclature pp t Temperature 2 Package 1 Range PX = FC-PBGA VT = FC-PBGA (lead free) Listings,” for more information on available package types Processor Platform 3 Frequency Frequency AJ = 533 MHz D = 266 MHz AK = 600 MHz E = 300 MHz AL = 667 MHz F = 333 MHz AP = 833 MHz AQ = 1000 MHZ Freescale Semiconductor r Revision 4 Level ...
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... CCCCC is the country of assembly. This space is left blank if parts are assembled in the United States. CCCCC is the country of assembly. This space is left blank if parts are assembled in the United States. Figure 53. Part Marking for FC-PBGA Device MPC8541E PowerQUICC™ III Integrated Communications Processor Hardware Specification, Rev. 4.2 Freescale Semiconductor Figure 53. MPC85nn ...
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... Device Nomenclature THIS PAGE INTENTIONALLY LEFT BLANK MPC8541E PowerQUICC™ III Integrated Communications Processor Hardware Specification, Rev. 4.2 86 Freescale Semiconductor ...
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... THIS PAGE INTENTIONALLY LEFT BLANK MPC8541E PowerQUICC™ III Integrated Communications Processor Hardware Specification, Rev. 4.2 Freescale Semiconductor Device Nomenclature 87 ...
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... Freescale Semiconductor product could create a situation where personal injury or death may occur. Should Buyer ...