GCIXP1200GC Intel, GCIXP1200GC Datasheet - Page 16

• Manufacturer Part Number: GCIXP1200GC
• Description: IC MPU NETWORK 232MHZ 432-BGA
• Manufacturer: Intel

Specifications of GCIXP1200GC

• Rohs Status: RoHS non-compliant
• Processor Type: Network
• Features: 32-bit StrongARM RISC Core
• Speed: 232MHz
• Voltage: 3.3V
• Mounting Type: Surface Mount
• Package / Case: 432-BGA
• Mounting: Surface Mount
• Operating Temperature (max): 70C
• Operating Temperature (min): 0C
• Operating Temperature Classification: Commercial
• Lead Free Status / Rohs Status: Not Compliant
• Other names: 839429

Intel
Errata
14.
Problem:
Implication:
Workaround:
Status:
15.
Problem:
Implication:
Workaround:
Status:
16.
Problem:
Implication:
Workaround:
Status:
17.
Problem:
Implication:
Workaround:
Status:
18.
Problem:
Implication:
Workaround:
Status:
16
®
IXP1200 Network Processor
FDAT and FBE# Signals After Reset
In Shared IX Bus mode, there may be a one cycle differential between when the master and slave
devices come out of reset.
For one cycle after reset, both devices may be driving the data bus high, FDAT[63:0], and the byte
enable signals, FBE#[7:0].
None
Fixed
Flow Control Data
Flow control data is driven onto the RDYBUS[7:0] pins for three cycles. While the flow control
enable signal is asserted only during the first cycle, the flow control data should be sampled on the
second cycle.
If the data is not stable, incorrect data may be transferred.
A NOP instruction should be is placed immediately prior to the flow control instruction in the
RDYBUS_TEMPLATE_PROG_x registers. When a NOP instruction is executed by the ReadyBus
Sequencer, the default data placed on the RDYBUS[7:0] is the flow control data. This will result in
the flow control data being driven on the bus during the NOP and the flow control instruction,
ensuring that the data is stable.
Fixed
Sixteen Quadword Transfers With SDRAM Instruction
Using the SDRAM instruction with either the r_fifo_rd or t_fifo_wr command, a 16 quadword
transfer is not valid.
Unpredictable results will occur.
To do 16 quadword transfers, utilize two 8 quadword transfers.
Fixed
BIST
In the BIST (Built-In Self Test) register, data lines [3:0] are improperly connected.
The BIST field can not be written, and, therefore, the BIST can not be performed.
Do not attempt to perform a BIST.
Fixed
Internal Arbiter
PCI Arbiter is arbitrating every cycle so that the grant signal is switching every clock cycle.
In cases where a master device takes more than 2 cycles to respond to a grant, if another device is
always requesting the bus in a faster manner, the slower device may not be granted access to the
bus.
Disable internal arbiter and use an external arbiter.
Fixed
Specification Update