GCIXP1200GC Intel, GCIXP1200GC Datasheet - Page 24

• Manufacturer Part Number: GCIXP1200GC
• Description: IC MPU NETWORK 232MHZ 432-BGA
• Manufacturer: Intel

Specifications of GCIXP1200GC

• Rohs Status: RoHS non-compliant
• Processor Type: Network
• Features: 32-bit StrongARM RISC Core
• Speed: 232MHz
• Voltage: 3.3V
• Mounting Type: Surface Mount
• Package / Case: 432-BGA
• Mounting: Surface Mount
• Operating Temperature (max): 70C
• Operating Temperature (min): 0C
• Operating Temperature Classification: Commercial
• Lead Free Status / Rohs Status: Not Compliant
• Other names: 839429

Intel
Errata
35.
Problem:
Implication:
Workaround:
24
®
IXP1200 Network Processor
PCI CSR (Control and Status Register) Access
StrongARM* core writes to any of the registers in the PCI Unit can get blocked if the write
coincides in time with a PCI Master-to-CSR access. The StrongARM* core does the write
operation, but the write data may not be written to the register.
The implications of this problem vary widely because of the number of PCI registers affected (a
total of 82 registers). Some examples are:
In general, the solution to the lost write problem is to write the register, then read it back and verify
that the write was successful. This works for the 66 of the 82 PCI registers that exhibit no side
effects from the write operation. The remaining 16 PCI registers have some degree of side effects
from a write operation. For registers with no side effects, a read to verify the write data is
unambiguous, so subsequent writes are attempted only when absolutely necessary. This is true even
if there is an arbitrary time between the write and the read, which could be the case if the
StrongARM* core is interrupted between these two operations.
The following table lists all CSRs that reside in the PCI unit. The table lists the type of bits in the
register -- Read/Write, Read Only, Write Only, Write-1-to-Clear, Write-1-to-Set. The table also lists
whether or not writes to the register have side effects. Entries that have side effects are shaded. If a
register has W1C and/or W1S bits, a write has the side effect of modifying those bits. However,
some registers with no W1C or W1S bits also have side effects. For each register with side effects
a potential workaround, if available, is provided in the paragraphs that follow.
PCI Configuration Registers - Accessible by Both PCI Master and StrongARM* Core
Vendor ID (PCI_VEN_DEV_ID)
Command (PCI_CMD_STAT)
Status (PCI_CMD_STAT)
Rev_ID (PCI_REV_CLASS)
Class Code (PCI_REV_CLASS)
Cache Line (PCI_CACHE_LAT_HDR_BIST)
Latency Timer (PCI_CACHE_LAT_HDR_BIST)
Header Type (PCI_CACHE_LAT_HDR_BIST)
BIST (PCI_CACHE_LAT_HDR_BIST)
Mem Base Address (PCI_MEM_BAR)
IO Base Address (PCI_IO_BAR)
DRAM Base Address (PCI_DRAM_BAR)
Subsys ID (PCI_SUBSYS)
Cap Pointer (PCI_CAP_PTR)
Int Line (PCI_INT_LAT)
Int Pin (PCI_INT_LAT)
1. Incorrect operation of DMA channels
2. Incorrect operation of PCI I
3. Incorrect operation of PCI interrupts
4. Incorrect operation of Timers 1 through 4
Register Name
2
O operations
0
4
6
8
9
C
D
E
F
10
14
18
2c
34
3c
3d
Offset
RO
RW/RO
RO/W1C
RO
RO
RW
RW
RO
RW
RW
RW
RW
RW
RW
RW
RW
Type
Specification Update
N
N
Y
N
N
N
N
N
N
N
N
N
N
N
N
N
Side Effects