Z8S18033FSC00TR Zilog, Z8S18033FSC00TR Datasheet - Page 38

• Manufacturer Part Number: Z8S18033FSC00TR
• Description: IC Z180 MPU 80QFP
• Manufacturer: Zilog

Specifications of Z8S18033FSC00TR

• Processor Type: Z180
• Speed: 33MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 80-BQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Features: -

When D6 is
basic clock rate, certain aspects of Power-Down modes, and
output drive/low-noise options (Figure 31).
bit is programmed as
as
If an external oscillator is used in divide-by-one mode, the
minimum pulse width requirement provided in the AC
Characteristics must be satisfied.
are both
ter
When D6 is
and executing a
into
output is blocked from the rest of the part, including
executing a
mode, in which the on-chip oscillator is stopped and the part
allows 2
when it restarts.
, the Z8S180/Z8L180 divides the frequency on the
Clock Divide Select. If this bit is
pin(s) by two to obtain its Master clock
without division.
17
0
bit (ICR5).
, a
mode in which the on-chip oscillator runs, but its
(128K) clock cycles for the oscillator to stabilize
or
0
1
and D3 is
instruction makes the Z8S180/Z8L180 en-
and D3 is
instruction puts the part into
instruction puts the Z8S180/Z8L180
1
, the part uses the
1
/
, setting the
0
, setting
This register controls the
Control. When these bits
mode, depending on the
0
, as it is after a
(ICR5) and
bit (ICR5)
frequency
. If this
out.
When D6 and D3 are both
executing a
is stopped, and the part allows only 64 clock cycles for the
oscillator to stabilize when it restarts.
The latter section,
scribes the subject more fully.
Z8S180/Z8L180 to honor a bus request during
mode. If this bit is set to
mode, a
timer is timed out.
is reduced to 33 percent of its drive capability.
Clock output. If this bit is set to
This bit controls the drive capability on the
T h i s b i t c o n t r o l s t h e a b i l i t y o f t h e
instruction puts the part into
is honored after the clock stabilization
mode, in which the on-chip oscillator
1
and
1
, setting
and the part is in
1
, the
Clock output
modes, de-
(
ZiLOG
) and