Z8S18033FSC00TR Zilog, Z8S18033FSC00TR Datasheet - Page 61

• Manufacturer Part Number: Z8S18033FSC00TR
• Description: IC Z180 MPU 80QFP
• Manufacturer: Zilog

Specifications of Z8S18033FSC00TR

• Processor Type: Z180
• Speed: 33MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 80-BQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Features: -

bit specifies the number of wait states introduced into CPU
or DMAC memory access cycles.
ZiLOG
The DMA/WAIT Control Register (
insertion of wait states into DMAC (and CPU) accesses of
memory or I/O. Also, the register defines the Request signal
to
fies the number of wait states introduced into CPU or DMAC
I/O access cycles.
and
channel 1 respectively. When reset to
sense. When set to
1
during
These wait states are added to the 3-clock I/O cycle that
is used to access the on-chip I/O registers. It is equally
valid to regard these as 0 to 3 wait states added to a 4-
clock external I/O cycle.
are cleared to
specify the DMA request sense for channel 0 and
1
.
, the input is edge sense.
0
and
during
are set to
.
0
, the input is level
and
1
during
This bit speci-
) controls the
are set
T h i s
and
.
for each channel as level or edge sense.
the DMA transfer mode for channel 1, which is limited to
memory to/from I/O transfers.
Typically, for an input/source device, the associated
bit should be programmed as
takes a relatively long time to update its Request signal after
the DMA channel reads data (in the first of the two machine
cycles involved in transferring a byte).
An output/destination device takes much less time to update
its Request signal after the DMA channel starts a
operation to it (the second machine cycle of the two cycles
involved in transferring a byte). With zero-wait state I/O cy-
cles, a device cannot update its request signal in the required
time, so edge sensing must be used.
A one-wait-state I/O cycle also does not provide sufficient
time for updating, so edge sensing is again required.
modifier for channel 1 memory to/from I/O transfer modes.
and
Specifies the source/destination and address
are cleared to
0
0
for level sense. The device
during
.
also sets