IDT79RC32T351-133DH IDT, Integrated Device Technology Inc, IDT79RC32T351-133DH Datasheet - Page 10

• Manufacturer Part Number: IDT79RC32T351-133DH
• Description: IC MPU 32BIT CORE 133MHZ 208-QFP
• Manufacturer: IDT, Integrated Device Technology Inc
• Series: Interprise™r

Specifications of IDT79RC32T351-133DH

• Processor Type: RISC 32-Bit
• Speed: 133MHz
• Voltage: 2.5V
• Mounting Type: Surface Mount
• Package / Case: 208-QFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Features: -
• Other names: 79RC32T351-133DH

EJTAG_TRST_N
JTAG_TRST_N
Debug
INSTP
CPUP
DMAP[0]
DMAP[1]
DMAP[2]
DMAP[3]
UART
U0SOUTP
U0SINP
U0RIN
U0DCRN
IDT 79RC32351
Name
Type I/O Type
O
O
O
O
O
O
I
I
I
I
I
I
Low Drive Instruction or Data Indicator. This signal is driven high during CPU instruction fetches and low during CPU data transac-
Low Drive CPU or DMA Transaction Indicator. This signal is driven high during CPU transactions and low during DMA transactions
Low Drive Active DMA channel code. DMA debug enable is selected during reset using the boot configuration and overrides the
Low Drive Active DMA channel code. DMA debug enable is selected during reset using the boot configuration and overrides the
Low Drive Active DMA channel code. DMA debug enable is selected during reset using the boot configuration and overrides the
Low Drive Active DMA channel code. DMA debug enable is selected during reset using the boot configuration and overrides the
STI
STI
STI
STI
STI
STI
EJTAG Test Reset. EJTAG_TRST_N is an active-low signal for asynchronous reset of only the EJTAG/ICE controller.
EJTAG_TRST_N requires an external pull-up on the board. EJTAG/ICE enable is selected during reset using the boot con-
figuration and overrides the selection of the Primary and Alternate functions. This signal requires an external resistor, listed
in Table 14.
Primary: General Purpose I/O, GPIOP[31]
1st Alternate function: DMA finished output, DMAFIN.
JTAG Test Reset. JTAG_TRST_N is an active-low signal for asynchronous reset of only the JTAG boundary scan control-
ler. JTAG_TRST_N requires an external pull-down on the board that will hold the JTAG boundary scan controller in reset
when not in use if selected. JTAG reset enable is selected during reset using the boot configuration and overrides the
selection of the Primary and Alternate functions.
Primary function: General Purpose I/O, GPIOP[2].
1st Alternate function: UART channel 0 ring indicator, U0RIN.
tions on the memory and peripheral bus.
on the memory and peripheral bus if CPU/DMA Transaction Indicator Enable is enabled. CPU/DMA Status mode enable is
selected during reset using the boot configuration and overrides the selection of the Primary and Alternate functions.
Primary function: General Purpose I/O, GPIOP[4].
1st Alternate function: UART channel 0 data terminal ready U0DTRN.
selection of the Primary and Alternate functions.
Primary function: General Purpose I/O, GPIOP[23].
1st Alternate function: TXADDR[1].
selection of the Primary and Alternate functions.
Primary function: General Purpose I/O, GPIOP[25].
1st Alternate function: RXADDR[1].
selection of the Primary and Alternate functions.
Primary function: General Purpose I/O, GPIOP[9].
1st Alternate function: U1SINP.
selection of the Primary and Alternate functions.
Primary function: General Purpose I/O, GPIOP[8].
1st Alternate function: U1SOUTP.
UART channel 0 serial transmit.
Primary function: General Purpose I/O, GPIOP[0]. At reset, this pin defaults to primary function GPIOP[0].
UART channel 0 serial receive.
Primary function: General Purpose I/O, GPIOP[1]. At reset, this pin defaults to primary function GPIOP[1].
UART channel 0 ring indicator.
Primary function: General Purpose I/O, GPIOP[2]. At reset, this pin defaults to primary function GPIOP[2] if JTAG reset
enable is not selected during reset using the boot configuration.
2nd Alternate function: JTAG boundary scan reset, JTAG_TRST_N.
UART channel 0 data carrier detect.
Primary function: General Purpose I/O, GPIOP[3]. At reset, this pin defaults to primary function GPIOP[3].
Table 1 Pin Descriptions (Part 6 of 7)
10 of 42
Description
May 25, 2004