IDT79RC32T351-133DH IDT, Integrated Device Technology Inc, IDT79RC32T351-133DH Datasheet - Page 6

• Manufacturer Part Number: IDT79RC32T351-133DH
• Description: IC MPU 32BIT CORE 133MHZ 208-QFP
• Manufacturer: IDT, Integrated Device Technology Inc
• Series: Interprise™r

Specifications of IDT79RC32T351-133DH

• Processor Type: RISC 32-Bit
• Speed: 133MHz
• Voltage: 2.5V
• Mounting Type: Surface Mount
• Package / Case: 208-QFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Features: -
• Other names: 79RC32T351-133DH

RWN
OEN
BWEN[3:0]
SDCSN[1:0]
RASN
CASN
SDWEN
CKENP
SDCLKINP
ATM Interface
ATMINP[11:0]
ATMIOP[1:0]
ATMOUTP[9:0]
TXADDR[1:0]
RXADDR[1:0]
General Purpose Input/Output
GPIOP[0]
GPIOP[1]
GPIOP[2]
GPIOP[3]
GPIOP[4]
IDT 79RC32351
Name
Type I/O Type
I/O
I/O
I/O
I/O
I/O
I/O
O
O
O
O
O
O
O
O
O
O
O
I
I
High Drive Read or Write. This signal indicates if the transaction on the memory and peripheral bus is a read transaction or a write
High Drive Output Enable. This signal is asserted low when data should be driven by an external device during device read transac-
High Drive SDRAM Byte Enable Mask or Memory and I/O Byte Write Enables. These signals are used as data input/output masks
High Drive SDRAM Chip Select. These signals are used to select the SDRAM device on the memory and peripheral bus. Each bit is
High Drive SDRAM Row Address Strobe. The row address strobe asserted low during memory and peripheral bus SDRAM transac-
High Drive SDRAM Column Address Strobe. The column address strobe asserted low during memory and peripheral bus SDRAM
High Drive SDRAM Write Enable. Asserted low during memory and peripheral bus SDRAM write transactions.
Low Drive SDRAM Clock Enable. Asserted high during active SDRAM clock cycles.
Low Drive
Low Drive ATM PHY Outputs. These pins are the outputs for the ATM interface.
Low Drive ATM Transmit Address [1:0]. 2-bit address bus used for transmission in Utopia-2 mode.
Low Drive ATM Receive Address [1:0]. 2-bit address bus for receiving in Utopia-2 mode.
Low Drive
Low Drive
Low Drive
Low Drive
Low Drive
with STI
with STI
with STI
with STI
with STI
with STI
STI
STI
transaction. A high level indicates a read from an external device, a low level indicates a write to an external device.
tions on the memory and peripheral bus.
during SDRAM transactions and as byte write enable signals during device controller transactions on the memory and
peripheral bus. They are active low.
BWEN[0] corresponds to byte lane MDATA[7:0].
BWEN[1] corresponds to byte lane MDATA[15:8].
BWEN[2] corresponds to byte lane MDATA[23:16].
BWEN[3] corresponds to byte lane MDATA[31:24].
asserted low during an access to the selected SDRAM.
tions.
transactions.
Primary function: General Purpose I/O, GPIOP[21].
SDRAM Clock Input. This clock input is a delayed version of SYSCLKP. SDRAM read data is sampled into the RC32351
on the rising edge of this clock.
ATM PHY Inputs. These pins are the inputs for the ATM interface.
ATM PHY Bidirectional Signals. These pins are the bidirectional pins for the ATM interface.
TXADDR[0] Primary function: General purpose I/O, GPIOP[22].
TXADDR[1] Primary function: General purpose I/O, GPIOP[23].
RXADDR[0] Primary function: General purpose I/O, GPIOP[24].
RXADDR[1] Primary function: General purpose I/O, GPIOP[25].
General Purpose I/O. This pin can be configured as a general purpose I/O pin.
Alternate function: UART channel 0 serial output, U0SOUTP.
General Purpose I/O. This pin can be configured as a general purpose I/O pin.
Alternate function: UART channel 0 serial input, U0SINP.
General Purpose I/O. This pin can be configured as a general purpose I/O pin.
1st Alternate function: UART channel 0 ring indicator, U0RIN.
2nd Alternate function: JTAG boundary scan tap controller reset, JTAG_TRST_N.
General Purpose I/O. This pin can be configured as a general purpose I/O pin.
Alternate function: UART channel 0 data carrier detect, U0DCRN.
General Purpose I/O. This pin can be configured as a general purpose I/O pin.
1st Alternate function: UART channel 0 data terminal ready, U0DTRN.
2nd Alternate function: CPU or DMA transaction indicator, CPUP.
Table 1 Pin Descriptions (Part 2 of 7)
6 of 42
Description
May 25, 2004