MPC850DEVR50BU Freescale Semiconductor, MPC850DEVR50BU Datasheet - Page 14

• Manufacturer Part Number: MPC850DEVR50BU
• Description: IC MPU PWRQUICC 50MHZ 256-PBGA
• Manufacturer: Freescale Semiconductor
• Series: PowerQUICC Ir

Specifications of MPC850DEVR50BU

• Processor Type: MPC8xx PowerQUICC 32-Bit
• Speed: 50MHz
• Voltage: 3.3V
• Mounting Type: Surface Mount
• Package / Case: 256-PBGA
• Family Name: MPC8xx
• Device Core: PowerQUICC
• Device Core Size: 32b
• Frequency (max): 50MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 3.3V
• Operating Supply Voltage (max): 3.465V
• Operating Supply Voltage (min): 3.135V
• Operating Temp Range: 0C to 95C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 256
• Package Type: BGA
• Core Size: 32 Bit
• Program Memory Size: 3KB
• Cpu Speed: 50MHz
• Embedded Interface Type: I2C, RS232, SPI, TDM, USB, UTOPIA
• Digital Ic Case Style: BGA
• No. Of Pins: 256
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: Compliant

Bus Signal Timing
14
Num
B28c
B28d
B29a
B29b
B29c
B29d
B29e
B29g
B29f
B29
MPC850 PowerQUICC™ Integrated Communications Processor Hardware Specifications, Rev. 2
CLKOUT falling edge to
WE[0–3] negated GPCM write
access TRLX = 0,1 CSNT = 1
write access TRLX = 0, CSNT =
1, EBDF = 1
CLKOUT falling edge to CS
negated GPCM write access
TRLX = 0,1 CSNT = 1, ACS =
10 or ACS = 11, EBDF = 1
WE[0–3] negated to D[0–31],
DP[0–3] high-Z GPCM write
access, CSNT = 0
WE[0–3] negated to D[0–31],
DP[0–3] high-Z GPCM write
access, TRLX = 0 CSNT = 1,
EBDF = 0
CS negated to D[0–31],
DP[0–3], high-Z GPCM write
access, ACS = 00, TRLX = 0 &
CSNT = 0
CS negated to D[0–31],
DP[0–3] high-Z GPCM write
access, TRLX = 0, CSNT = 1,
ACS = 10 or ACS = 11, EBDF =
0
WE[0–3] negated to D[0–31],
DP[0–3] high-Z GPCM write
access, TRLX = 1, CSNT = 1,
EBDF = 0
CS negated to D[0–31],
DP[0–3] high-Z GPCM write
access, TRLX = 1, CSNT = 1,
ACS = 10 or ACS = 11, EBDF =
0
WE[0–3] negated to D[0–31],
DP[0–3] high-Z GPCM write
access TRLX = 0, CSNT = 1,
EBDF = 1
CS negated to D[0–31],
DP[0–3] high-Z GPCM write
access TRLX = 0, CSNT = 1,
ACS = 10 or ACS = 11, EBDF =
1
Characteristic
Table 6. Bus Operation Timing
28.00
28.00
7.00
3.00
8.00
3.00
8.00
5.00
5.00
Min
—
50 MHz
14.00 11.00 18.00
14.00
Max
—
—
—
—
—
—
—
—
13.00
13.00
43.00
43.00
6.00
6.00
9.00
9.00
Min
—
66 MHz
18.00
Max
—
—
—
—
—
—
—
—
1
(continued)
36.00
36.00
11.00
11.00
9.00
4.00
4.00
7.00
7.00
Min
—
80 MHz
16.00
16.00
Max
—
—
—
—
—
—
—
—
FFACT
0.375
0.375
0.250
0.500
0.250
0.500
1.500
1.500
0.375
0.375
Freescale Semiconductor
Cap Load
(default
50 pF)
50.00
50.00
50.00
50.00
50.00
50.00
50.00
50.00
50.00
50.00
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns