PRIXP425BC Intel, PRIXP425BC Datasheet - Page 41

• Manufacturer Part Number: PRIXP425BC
• Description: IC NETWRK PROCESSR 400MHZ 492BGA
• Manufacturer: Intel

Specifications of PRIXP425BC

• Processor Type: Network
• Features: XScale Core
• Speed: 400MHz
• Voltage: 1.3V
• Mounting Type: Surface Mount
• Package / Case: 492-BGA
• Core Operating Frequency: 400MHz
• Package Type: BGA
• Pin Count: 492
• Mounting: Surface Mount
• Operating Temperature (max): 70C
• Operating Temperature (min): 0C
• Operating Temperature Classification: Commercial
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 869083

Intel
Table 11.
August 2006
Document Number: 252479-006US
®
IXP42X product line and IXC1100 control plane processors
MII Interfaces (Sheet 2 of 2)
ETH_TXCLK1
ETH_TXDATA1[3:0]
ETH_TXEN1
ETH_RXCLK1
ETH_RXDATA1[3:0]
ETH_RXDV1
ETH_COL1
ETH_CRS1
†
††
Name
For a legend of the Type codes, see
For new designs, this signal should be pulled high with a 10-KΩ resistor when not being utilized in the
system. No change is required to existing designs that have this signal pulled low.
Power
or Sys
Intel
Reset
Reset
Z
Z
Z
Z
Z
Z
Z
Z
®
IXP42X Product Line of Network Processors and IXC1100 Control Plane Processor
Reset
Post
VI
VI
VI
VI
VI
VI
0
0
Type
O
O
I
I
I
I
I
I
Table 5 on page
†
Externally supplied transmit clock.
Should be pulled high
being utilized in the system.
Transmit data bus to PHY, asserted synchronously with
respect to ETH_TXCLK1.
Indicates that the PHY is being presented with nibbles on
the MII interface. Asserted synchronously, with respect to
ETH_TXCLK1, at the first nibble of the preamble, and
remains asserted until all the nibbles of a frame are
presented.
Externally supplied receive clock.
Should be pulled high
being utilized in the system.
Receive data bus from PHY, data sampled synchronously,
with respect to ETH_RXCLK1.
Receive data valid, used to inform the MII interface that the
Ethernet PHY is sending data.
Should be pulled high
being utilized in the system.
Asserted by the PHY when a collision is detected by the
PHY.
Asserted by the PHY when the transmit medium or receive
medium are active. De-asserted when both the transmit
and receive medium are idle. Remains asserted throughout
the duration of collision condition. PHY asserts CRS
asynchronously and de-asserts synchronously with respect
to ETH_RXCLK1.
Should be pulled high
being utilized in the system.
• 25 MHz for 100 Mbps operation
• 2.5 MHz for 10 Mbps
• 25 MHz for 100 Mbps operation
• 2.5 MHz for 10 Mbps
• Should be pulled high
• Should be pulled low through a 10-KΩ resistor when
not being utilized in the system.
not being utilized in the system.
33.
††
††
††
††
Description
through a 10-KΩ resistor when not
through a 10-KΩ resistor when not
through a 10-KΩ resistor when not
through a 10-KΩ resistor when not
††
through a 10-KΩ resistor when
Datasheet
41