PRIXP425BC Intel, PRIXP425BC Datasheet - Page 51

• Manufacturer Part Number: PRIXP425BC
• Description: IC NETWRK PROCESSR 400MHZ 492BGA
• Manufacturer: Intel

Specifications of PRIXP425BC

• Processor Type: Network
• Features: XScale Core
• Speed: 400MHz
• Voltage: 1.3V
• Mounting Type: Surface Mount
• Package / Case: 492-BGA
• Core Operating Frequency: 400MHz
• Package Type: BGA
• Pin Count: 492
• Mounting: Surface Mount
• Operating Temperature (max): 70C
• Operating Temperature (min): 0C
• Operating Temperature Classification: Commercial
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 869083

Documentation Changes
1.
Issue:
Affected Docs:
2.
Issue:
Affected Docs:
3.
Issue:
Affected Docs:
4.
Issue:
Intel
®
IXP42X Product Line of Network Processors and IXC1100 Control Plane Processor
Correction to Expansion Bus Label (SCR 3888)
In the Intel
Developer’s Manual (page 300, Figure 59), the Expansion Bus Peripheral Connection diagram
incorrectly labels the Expansion Bus on the processor as EX_ADDR[3:0].
EX_ADDR[3:0] should be changed to EX_ADDR[23:0].
Intel
Developer’s Manual (252480-003)
Correction to Input Reference Slew Rate in a Oscillator Configuration (SCR
3890)
In the Intel
Datasheet, Figures 38 and 39, the note “Note 4. The reference-clock input slope should not exceed
more than 2.5 V/nS to ensure proper PLL operation.” is incomplete.
Replace note 4 with the following statement: “Note 4. Where the IXP42X is configured with an
input reference-clock, the slew rate should never be faster than 2.5 V/nS to ensure proper PLL
operation. To properly guarantee PLL operation at the slower slew rate, the Vih and Vil levels need
to be met at the 33.33 MHz frequency.”
Intel
Datasheet (252479-004)
Update of Management Data Output Register (SCR 4053)
In the Intel
Datasheet, the requirement for a 1.5K pull-up resistor on the ETH_MDIO needs to be added to
Table 9 on page 36.
The table should read: “ETH_MDIO Management data output. Provides the write data to both
PHY devices connected to each MII interface. Requires a 1.5K pull-up resistor.
Should be pulled low through a 10-K resistor when not being utilized in the system.”
Intel
Datasheet (252479-004)
Update of Core Clock Speed Expansion Bus Configuration Table (SCR 4086)
In the Intel
Developer’s Manual (page 324), Table 124, “Setting the Intel XScale Core Operation Speed”, is
incomplete. Not all the possible expansion bus (core clock speed) configurations are listed.
Replace Table 124 with the following table:
®
®
®
IXP42X Product Line of Network Processors and IXC1100 Control Plane Processor
IXP42X Product Line of Network Processors and IXC1100 Control Plane Processor
IXP42X Product Line of Network Processors and IXC1100 Control Plane Processor
®
®
®
®
IXP42X Product Line of Network Processors and IXC1100 Control Plane Processor
IXP42X Product Line of Network Processors and IXC1100 Control Plane Processor
IXP42X Product Line of Network Processors and IXC1100 Control Plane Processor
IXP42X Product Line of Network Processors and IXC1100 Control Plane Processor
Documentation Changes
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