MPC850VR50BU Freescale Semiconductor, MPC850VR50BU Datasheet - Page 18

• Manufacturer Part Number: MPC850VR50BU
• Description: IC MPU PWRQUICC 50MHZ 256-PBGA
• Manufacturer: Freescale Semiconductor

Specifications of MPC850VR50BU

• Processor Type: MPC8xx PowerQUICC 32-Bit
• Speed: 50MHz
• Voltage: 3.3V
• Mounting Type: Surface Mount
• Package / Case: 256-PBGA
• Leaded Process Compatible: Yes
• Rohs Compliant: Yes
• Peak Reflow Compatible (260 C): Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -

Bus Signal Timing
18
1
For a frequency F, the following equations should be applied to each one of the above parameters:
For minima:
For maxima:
where:
D is the parameter value to the frequency required in ns
F is the operation frequency in MHz
D
CAP LOAD is the capacitance load on the signal in question.
FFACTOR is the one defined for each of the parameters in the table.
2
3
4
5
6
7
8
9
10
11
Num
50
B42
B43
the part, new bus timing must be calculated for all frequency-dependent AC parameters. Frequency-dependent AC
parameters are those with an entry in the FFactor column. AC parameters without an FFactor entry do not need to
be calculated and can be taken directly from the frequency column corresponding to the frequency marked on the
part. The following equations should be used in these calculations.
values in one cycle) or the frequency of the jitter is fast (i.e., it does not stay at an extreme value for a long time) then
the maximum allowed jitter on EXTAL can be up to 2%.
BG output is relevant when the MPC850 is selected to work with internal bus arbiter.
not when the memory controller or the PCMCIA interface drives them).
timing for BG input is relevant when the MPC850 is selected to work with the external bus arbiter.
signal is asserted.
read accesses controlled by chip-selects controlled by the UPM in the memory controller, for data beats where DLT3
= 1 in the UPM RAM words. (This is only the case where data is latched on the falling edge of CLKOUT.
B37 and B38 are specified to enable the freeze of the UPM output signals.
The minima provided assume a 0 pF load, whereas maxima assume a 50pF load. For frequencies not marked on
Phase and frequency jitter performance results are valid only if the input jitter is less than the prescribed value.
If the rate of change of the frequency of EXTAL is slow (i.e. it does not jump between the minimum and maximum
The timing for BR output is relevant when the MPC850 is selected to work with external bus arbiter. The timing for
The setup times required for TA, TEA, and BI are relevant only when they are supplied by an external device (and
The timing required for BR input is relevant when the MPC850 is selected to work with the internal bus arbiter. The
The D[0–31] and DP[0–3] input timings B20 and B21 refer to the rising edge of the CLKOUT in which the TA input
The D[0:31] and DP[0:3] input timings B20 and B21 refer to the falling edge of CLKOUT. This timing is valid only for
The timing B30 refers to CS when ACS = '00' and to WE[0:3] when CSNT = '0'.
The signal UPWAIT is considered asynchronous to CLKOUT and synchronized internally. The timings specified in
The AS signal is considered asynchronous to CLKOUT.
is the parameter value defined for 50 MHz
D =
D =
MPC850 PowerQUICC™ Integrated Communications Processor Hardware Specifications, Rev. 2
FFACTOR x 1000
FFACTOR x 1000
CLKOUT rising edge to TS valid
(hold time)
AS negation to memory
controller signals negation
F
F
Characteristic
+
+
(D
(D
50
50
Table 6. Bus Operation Timing
- 20 x FFACTOR)
-20 x FFACTOR)
2.00
Min
—
50 MHz
Max
TBD
—
+
1ns(CAP LOAD - 50) / 10
2.00
Min
—
66 MHz
Max
TBD
—
1
(continued)
TBD
2.00
Min
80 MHz
Max
—
—
FFACT
—
—
Freescale Semiconductor
Cap Load
(default
50 pF)
50.00
50.00
Unit
ns
ns