MPC850VR50BU Freescale Semiconductor, MPC850VR50BU Datasheet - Page 31

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MPC850VR50BU

Manufacturer Part Number
MPC850VR50BU
Description
IC MPU PWRQUICC 50MHZ 256-PBGA
Manufacturer
Freescale Semiconductor
Datasheet

Specifications of MPC850VR50BU

Processor Type
MPC8xx PowerQUICC 32-Bit
Speed
50MHz
Voltage
3.3V
Mounting Type
Surface Mount
Package / Case
256-PBGA
Leaded Process Compatible
Yes
Rohs Compliant
Yes
Peak Reflow Compatible (260 C)
Yes
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Features
-

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0
Table 7
Figure 22
Figure 23
Freescale Semiconductor
1
The timings I41, I42, and I43 are specified to allow the correct function of the IRQ lines detection circuitry, and has no
Num
level sensitive. The IRQ lines are synchronized internally and do not have to be asserted or negated with reference
to the CLKOUT.
direct relation with the total system interrupt latency that the MPC850 is able to support
The timings I39 and I40 describe the testing conditions under which the IRQ lines are tested when being defined as
I39
I40
I41
I42
I43
provides interrupt timing for the MPC850.
CLKOUT
CLKOUT
MPC850 PowerQUICC™ Integrated Communications Processor Hardware Specifications, Rev. 2
provides the interrupt detection timing for the external level-sensitive lines.
provides the interrupt detection timing for the external edge-sensitive lines.
IRQx valid to CLKOUT rising edge (set up time)
IRQx hold time after CLKOUT.
IRQx pulse width low
IRQx pulse width high
IRQx edge-to-edge time
IRQx
IRQx
Figure 22. Interrupt Detection Timing for External Level Sensitive Lines
Figure 23. Interrupt Detection Timing for External Edge Sensitive Lines
Characteristic
1
Table 7. Interrupt Timing
I39
I39
I43
I41
80.00
6.00
2.00
3.00
3.00
Min
50 MHz
I40
Max
I43
121.0
6.00
2.00
3.00
3.00
Min
66MHz
I42
Max
100.0
6.00
2.00
3.00
3.00
Min
80 MHz
Max
Bus Signal Timing
Unit
ns
ns
ns
ns
ns
31

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