MPC5200CBV400 Freescale Semiconductor, MPC5200CBV400 Datasheet - Page 36

• Manufacturer Part Number: MPC5200CBV400
• Description: IC MPU 32BIT 400MHZ PPC 272-PBGA
• Manufacturer: Freescale Semiconductor

Specifications of MPC5200CBV400

• Processor Type: MPC52xx PowerPC 32-Bit
• Speed: 400MHz
• Voltage: 1.5V
• Mounting Type: Surface Mount
• Package / Case: 272-PBGA
• Core Size: 32 Bit
• No. Of I/o's: 56
• Ram Memory Size: 16KB
• Cpu Speed: 400MHz
• No. Of Timers: 8
• Embedded Interface Type: CAN, I2C, SPI, UART, USB
• No. Of Pwm Channels: 8
• Digital Ic Case Style: BGA
• Rohs Compliant: No
• Family Name: MPC52xx
• Device Core: PowerPC
• Device Core Size: 32b
• Frequency (max): 400MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 1.5V
• Operating Supply Voltage (max): 1.58V
• Operating Supply Voltage (min): 1.42V
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 272
• Package Type: BGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Features: -
• Lead Free Status / Rohs Status: Not Compliant

Electrical and Thermal Characteristics
36
(t)
(t)
(t)
Name
(t)
(t)
(t)
NOTE: The directionof signalassertionis towardsthe
top of the page, and the direction of negation is
towards the bottom of the page, irrespective of the
electrical properties of the signal.
(t)
(t)
2CYC
2CYC
CYC
DVS
DVH
DH
DS
FS
DMACK
DMARQ
(Drive)
(Host)
RDATA
(Drive)
WDATA
(Host)
DIOR
DIOW
(Host)
Min
240
114
235
15
70
MODE 0
5
6
0
(ns)
Max
230
—
—
—
—
—
—
—
Min
160
156
10
75
48
MODE 1
5
6
0
tI
(ns)
tC
Table 29. Ultra DMA Timing Specification
Max
200
—
—
—
—
—
—
—
tE
Figure 16. Multiword DMA Timing
tD
tG
Min
120
117
55
34
MODE 2
7
5
6
0
MPC5200 Data Sheet, Rev. 4
(ns)
Max
170 First STROBE time for drive to first negate DSTROBE
—
—
—
—
—
—
—
t0
tF
tH
Typical sustained average two cycle time.
For information only, do not test.
Cycle time allowing for asymmetry and clock
variations from STROBE edge to STROBE edge
Two-cycle time allowing for clock variations, from
rising edge to next rising edge or from falling edge to
next falling edge of STROBE.
Data setup time at recipient.
Data hold time at recipient.
Data valid setup time at sender, to STROBE edge.
Data valid hold time at sender, from STROBE edge.
from STOP during a data-in burst.
tK
tS
Comment
tL
tJ
Freescale Semiconductor
SpecID
A8.26
A8.27
A8.28
A8.29
A8.30
A8.31
A8.33
A8.32