MC68EC040RC25A Freescale Semiconductor, MC68EC040RC25A Datasheet - Page 241

• Manufacturer Part Number: MC68EC040RC25A
• Description: IC MPU 32BIT 25MHZ 179-PGA
• Manufacturer: Freescale Semiconductor

Specifications of MC68EC040RC25A

• Processor Type: M680x0 32-Bit
• Speed: 25MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 179-PGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Features: -

Freescale Semiconductor, Inc.
for the pending exception. The processor sets only one of the continuation bits when the
access error stack frame is created. If the access error exception handler sets multiple
bits, operation of the RTE instruction is undefined.
If the frame format field in the stack frame contains an illegal format code, a format
exception occurs. If a format error or access fault exception occurs during the frame
validation sequence of the RTE instruction, the processor creates a normal four-word or
an access error stack frame below the frame that it was attempting to use. The illegal
stack frame remains intact, so that the exception handler can examine or repair the illegal
frame. In a multiprocessor system, the illegal frame can be left so that, when appropriate,
another processor of a different type can use it.
The bus error exception handler can identify bus error exceptions due to instruction faults
by examining the TM field in the SSW of the access error stack frame. For user and
supervisor instruction faults, the TM field contains $2 and $6, respectively (see Figure
8-7). Since the processor allows all pending accesses to complete before reporting an
instruction fault, the stack frame for an instruction fault will not contain any pending write-
backs. The ATC bit of the SSW is used to distinguish between ATC faults and physical
bus errors, and the FA field contains the logical address of the instruction prefetch. For
ATC faults, the exception handler can execute a PTEST instruction (using the FA and TM
fields from the SSW) to determine the specific cause of the address translation failure.
After the handler corrects the cause of the fault, it executes an RTE instruction to restart
execution of the instruction that contained the faulted prefetch.
For an address error fault, the processor saves a format $2 exception stack frame on the
stack. This stack frame contains the PC pointing to the instruction that caused the address
error as well as the actual address referenced by the instruction. Note that bit 0 of the
referenced address is cleared on the stack frame. Address error faults must be repaired in
software.
For a fault due to a data ATC fault or bus error, pending write-backs are also saved on the
access error stack frame and must be completed by the exception handler. For the faulted
access, the fault address in the FA field combined with the transfer attribute information
from the SSW can be used to identify the cause of the fault. In identifying the fault, the
system programmer should be aware that the data memory unit considers the read portion
of read-modify-write transfers (for TAS, CAS, CAS2, and some translation table updates)
a write. This prevents both read and write accesses from occurring unless all pages
touched by the instruction or table update are write enabled.
All accesses other than instruction prefetches go through the data memory unit, and the
M68040 treats the instruction and data address spaces as a single merged address space
(the exception is the presence of separate transparent translation registers). The function
codes for accesses such as PC relative operand addressing and MOVES transfers to
function codes $2 and $6 (user and supervisor instruction spaces in the MC68000) are
converted to data references to go through the data memory unit, and appear in the TM
field of the access error stack frame as data references.
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M68040 USER’S MANUAL
MOTOROLA
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