MC68030RC25C Freescale Semiconductor, MC68030RC25C Datasheet - Page 320

• Manufacturer Part Number: MC68030RC25C
• Description: IC MPU 32BIT ENHANCED 128-PGA
• Manufacturer: Freescale Semiconductor

Specifications of MC68030RC25C

• Processor Type: M680x0 32-Bit
• Speed: 25MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 128-PGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -

MOTOROLA
WP - - WRITE PROTECT
Each logical portion of an entry has a corresponding 28-bit physical (or data)
portion. The physical portion contains these fields:
CI - - CACHE INHIBIT
M - - MODIFIED
27
- - BUS ERROR
the original write access to be performed. This assures that the first write
This bit is set for an entry if a bus error, an invalid descriptor, a supervisor
violation, or a limit violation is encountered during the table search cor-
set until a PFLUSH instruction or a PLOAD instruction for this entry inval-
This bit is set when the cache inhibit bit of the page descriptor correspond-
This bit is set when a WP bit is set in any of the descriptors encountered
write protects all pages accessed with that descriptor. When the WP bit is
set, a write access or a read-modify-write access to the logical address
corresponding to this entry causes a bus error exception to be taken im-
This bit is set when a valid write access to the logical address corresponding
to the entry occurs. If the M bit is clear and a write access to this logical
address is attempted, the MC68030 aborts the access and initiates a table
search, setting the M bit in the page descriptor, invalidating the old ATC
entry, and creating a new entry with the M bit set. The MMU then allows
operation to a page sets the M bit in both the ATC and the page descriptor
responding to this entry. When B is set, a subsequent access to the logical
address causes the MC68030 to take a bus error exception. Since an ATC
miss causes an immediate retry of the access after the table search op-
eration, the bus error exception is taken on the retry. The B bit remains
idates the entry or until the replacement algorithm for the ATC replaces it.
ing to this entry is set. When the MC68030 accesses the logical address of
an entry with the CI bit set, it asserts the cache inhibit out signal (CLOUT)
during the corresponding bus cycle. This signal inhibits caching in the on-
chip caches and can also be used for external caches.
during the table search for this entry. Setting a WP bit in a table descriptor
mediately.
in the translation tables even when a previous read operation to the page
had created an entry for that page in the ATC with the M bit clear.
26
25
24
23
MC68030 USER'S MANUAL
PHYSICAL ADDRESS
9-19
0
I
9