MC68030RC25C Freescale Semiconductor, MC68030RC25C Datasheet - Page 440

• Manufacturer Part Number: MC68030RC25C
• Description: IC MPU 32BIT ENHANCED 128-PGA
• Manufacturer: Freescale Semiconductor

Specifications of MC68030RC25C

• Processor Type: M680x0 32-Bit
• Speed: 25MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 128-PGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -

MOTOROLA
I cA I Pc I °" I o I 0 I 0 I 0 I
tions. If the coprocessor issues this primitive during the execution of a
conditional category instruction, the main processor initiates protocol vio-
lation exception processing. Figure 10-37 shows the format of the transfer
multiple coprocessor registers primitive.
trol alterable and predecrement addressing modes are valid. Invalid address-
This primitive uses the CA, PC, and DR bits as previously described.
transferred. The operand length must be an even number of bytes; odd length
operands cause the MC68030 to initiate protocol violation exception pro-
cessing (refer to 10.5.2.1 PROTOCOL VIOLATIONS).
When the main processor reads this primitive, it calculates the effective ad-
to the first of any necessary effective address extension words when this
for each extension word referenced during the effective address calculation.
trol addressing modes and the postincrement addressing mode are valid.
emulator exception processing (refer to 10.5.2.2 F-LINE EMULATOR EXCEP-
TIONS).
After performing the effective address calculation, the MC68030 reads a
the register select mask to specify the number of operands to transfer; the
the number of operands. The order of the ones in the register select mask
erands can be transferred by the main processor in response to this primitive.
The total number of bytes transferred is the product of the number of op-
erands transferred and the length of each operand specified in bits [0-7] of
the primitive format.
Bits [7-0] of the primitive format indicate the length in bytes of each operand
dress specified in the coprocessor instruction. The scanPC should be pointing
primitive is read from the response CIR; the scanPC is incremented by two
For transfers from the coprocessor to the effective address (DR = 1 ), the con-
ing modes cause the MC68030 to abort the instruction by writing an abort
mask (refer to 10.3.2 Control CIR) to the control CIR and to initiate F-line
MC68030 counts the number of ones in the register select mask to determine
is not relevant to the operation of the main processor. As many as 16 op-
For transfers from the effective address to the coprocessor (DR=0), the con-
16-bit register select mask from the register select CIR. The coprocessor uses
15
Figure 10-37. Transfer Multiple Coprocessor Registers Primitive Format
14
13
12
11
MC68030 USER'S MANUAL
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10-53
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