MPC8255AZUMHBB Freescale Semiconductor, MPC8255AZUMHBB Datasheet - Page 6

• Manufacturer Part Number: MPC8255AZUMHBB
• Description: IC MPU POWERQUICC II 480-TBGA
• Manufacturer: Freescale Semiconductor

Specifications of MPC8255AZUMHBB

• Processor Type: MPC82xx PowerQUICC II 32-bit
• Speed: 266MHz
• Voltage: 2V
• Mounting Type: Surface Mount
• Package / Case: 480-TBGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Features: -

Features
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— Operates with FCC2 (UTOPIA 8)
— Provides serial loop back mode
— Cell echo mode is provided
— Supports both FCC transmit modes
— Supports TC-layer and PMD-WIRE interface (according to the ATM-Forum af-phy-0063.000)
— Cell counters for performance monitoring
— Overrun (Rx cell FIFO) and underrun (Tx cell FIFO) condition produces maskable interrupt
— May be operated at E1 and DS-1 rates. In addition, xDSL applications at bit rates up to 10 Mbps
PCI bridge (MPC8265 and MPC8266 only)
— PCI Specification Revision 2.2 compliant and supports frequencies up to 66 MHz
— On-chip arbitration
— Support for PCI to 60x memory and 60x memory to PCI streaming
— PCI Host Bridge or Periphera
— Includes 4 DMA channels for the following transfers:
— Includes all of the configuration registers (which are automatically loaded from the EPROM
— Supports the I
MPC8260A PowerQUICC™ II Integrated Communications Processor Hardware Specifications, Rev. 1.1
– External rate mode—Idle cells are generated by the FCC (microcode) to control data rate.
– Internal rate mode (sub-rate)—FCC transfers only the data cells using the required data rate.
– 16-bit counters count
– Maskable interrupt is sent to the host when a counter expires
are supported
– PCI-to-60x to 60x-to-PCI
– 60x-to-PCI to PCI-to-60x
– PCI-to-60x to PCI-to-60x
– 60x-to-PCI to 60x-to-PCI
and used to configure the MPC8265) required by the PCI standard as well as message and
doorbell registers
- Coset removing (programmable by the user)
- Filtering idle/unassigned cells (programmable by the user)
- Performing HEC error detection and single bit error correction (programmable by user)
- Generating loss of cell delineation status/interrupt (LOC/LCD)
The TC layer generates idle/unassigned cells to maintain the line bit rate.
- HEC error cells
- HEC single bit error and corrected cells
- Idle/unassigned cells filtered
- Idle/unassigned cells transmitted
- Transmitted ATM cells
- Received ATM cells
2
O standard
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capabilities
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