MPC8540PX833LB Freescale Semiconductor, MPC8540PX833LB Datasheet - Page 15

• Manufacturer Part Number: MPC8540PX833LB
• Description: IC MPU 32BIT 833MHZ 783-FCPBGA
• Manufacturer: Freescale Semiconductor

Specifications of MPC8540PX833LB

• Processor Type: MPC85xx PowerQUICC III 32-Bit
• Speed: 833MHz
• Voltage: 1.2V
• Mounting Type: Surface Mount
• Package / Case: 783-FCPBGA
• Family Name: MPC85XX
• Device Core: PowerQUICC III
• Device Core Size: 32b
• Frequency (max): 833MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 1.2V
• Operating Supply Voltage (max): 1.26V
• Operating Supply Voltage (min): 1.14V
• Operating Temp Range: 0C to 105C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 783
• Package Type: FCBGA
• For Use With: MPC8548CDS - DEV TOOLS CDS FOR 8548MPC8540ADS-BGA - BOARD APPLICATION DEV 8540CWH-PPC-8540N-VE - KIT EVAL SYSTEM MPC8540
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Features: -
• Lead Free Status / Rohs Status: Not Compliant

MPC8540 Architecture Overview
3.12 Integrated DMA
The MPC8540 DMA engine is capable of transferring blocks of data from any legal address range to any other legal
address range. Therefore, it can perform a DMA transfer between any of its I/O or memory ports or even between
two devices or locations on the same port.
The four-channel DMA controller allows chaining (both extended and direct) through local memory-mapped chain
descriptors. Scattering, gathering, and misaligned transfers are supported. In addition, advanced capabilities such as
stride transfers and complex transaction chaining are supported.
DMA transfers can be initiated by a single write to a configuration register. There is also support for external control
of transfers using DMA_DREQ, DMA_DACK, and DMA_DDONE handshake signals.
DMA descriptors encompass a rich set of attributes that allow DMA transfers to bypass outbound address translation
and supply external addresses and attributes directly to the RapidIO port. Local attributes such as snoop and L2-write
stashing can be specified by descriptors.
Interrupts are provided on a completed segment, link, list, chain, or on an error condition. Coherency is selectable
and hardware enforced (snoop/no snoop).
3.13 PCI Controller
The MPC8540 64-bit PCI controller is compatible with the PCI Local Bus Specification, Revision 2.2 and the PCI-X
Addendum, Revision 1.0. The interface can function as a host or agent bridge interface in either PCI or PCI-X mode.
Both PCI and PCI-X modes support 64-bit addressing and 32-bit or 64-bit data buses.
As a master, the MPC8540 supports read and write operations to the PCI memory space, the PCI I/O space, and the
PCI configuration space. Also, the MPC8540 can generate PCI special-cycle and interrupt-acknowledge commands.
As a target, the MPC8540 supports read and write operations to system memory as well as configuration accesses.
PCI-X functionality includes split transaction support for four outstanding split transactions. Split response data is
returned in order without interleaving. As a target, the MPC8540 supports all PCI-X sizes. As a master it internally
combines transactions up to 256 bytes.
An internal arbiter can be used to support up to five external masters. A round robin arbitration algorithm with two
priority levels is used.
3.14 RapidIO Controller
The RapidIO interconnect unit on the MPC8540 is based on the RapidIO Interconnect Specification, Revision 1.1.
RapidIO is a high-performance, point-to-point, low-pin-count, packet-switched system-level interconnect that can
be used in a variety of applications as an open standard. The RapidIO architecture provides a rich variety of features
including high data bandwidth, low-latency capability, and support for high-performance I/O devices, as well as
providing message-passing and software-managed programming models.
The RapidIO unit on the MPC8540 supports the I/O and message-passing logical specifications, the common
transport specification, and the 8/16 LP-LVDS physical layer specification of the RapidIO Interconnect
Specification. It does not support the globally shared memory logical specification.
Highlights of the implementation include: support for four priority levels and ordering within a priority level, CRC
error management, 32- to 256-byte transactions and 8-bit data width ports.
The physical layer of the RapidIO unit can operate at up to 500 MHz. Because the interface is defined as a
source-synchronous, double-data-rate, LVDS-signaling interconnect, the theoretical unidirectional peak bandwidth
MPC8540 PowerQUICC III™ Integrated Host Processor Product Brief, Rev. 0.1
Freescale Semiconductor
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