MC68020RC33E Freescale Semiconductor, MC68020RC33E Datasheet - Page 162

• Manufacturer Part Number: MC68020RC33E
• Description: IC MICROPROCESSOR 32BIT 114-PGA
• Manufacturer: Freescale Semiconductor

Specifications of MC68020RC33E

• Processor Type: M680x0 32-Bit
• Speed: 33MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 114-PGA
• Family Name: M68000
• Device Core: ColdFire
• Device Core Size: 32b
• Frequency (max): 33.33MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 5V
• Operating Supply Voltage (max): 5.25V
• Operating Supply Voltage (min): 4.75V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Through Hole
• Pin Count: 114
• Package Type: PGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: Compliant

Freescale Semiconductor, Inc.
the coprocessor requests that the MC68020/EC020 calculate an effective address during
coprocessor instruction execution, information required for the calculation must be
included in the instruction format as effective address extension words.
7.2.1.2 PROTOCOL. The execution of a cpGEN instruction follows the protocol shown in
Figure 7-7. The main processor initiates communication with the coprocessor by writing
the instruction command word to the command CIR. The coprocessor decodes the
command word to begin processing the cpGEN instruction. Coprocessor design
determines the interpretation of the coprocessor command word; the MC68020/EC020
does not attempt to decode it.
While the coprocessor is executing an instruction, it requests any required services from
and communicates status to the main processor by placing coprocessor response
primitive codes in the response CIR. After writing to the command CIR, the main
processor reads the response CIR and responds appropriately. When the coprocessor
has completed the execution of an instruction or no longer needs the services of the main
processor to execute the instruction, it provides a response to release the main processor.
The main processor can then execute the next instruction in the instruction stream.
However, if a trace exception is pending, the MC68020/EC020 does not terminate
communication with the coprocessor until the coprocessor indicates that it has completed
all processing associated with the cpGEN instruction (refer to 7.5.2.5 Trace Exceptions).
The coprocessor interface protocol shown in Figure 7-7 allows the coprocessor to define
the operation of each coprocessor general type instruction. That is, the main processor
initiates the instruction execution by writing the instruction command word to the
command CIR and by reading the response CIR to determine its next action. The
execution of the coprocessor instruction is then defined by the internal operation of the
coprocessor and by its use of response primitives to request services from the main
processor. This instruction protocol allows a wide range of operations to be implemented
in the general instruction category.
MOTOROLA
M68020 USER’S MANUAL
7- 9
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