MC68020RC33E Freescale Semiconductor, MC68020RC33E Datasheet - Page 176

• Manufacturer Part Number: MC68020RC33E
• Description: IC MICROPROCESSOR 32BIT 114-PGA
• Manufacturer: Freescale Semiconductor

Specifications of MC68020RC33E

• Processor Type: M680x0 32-Bit
• Speed: 33MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 114-PGA
• Family Name: M68000
• Device Core: ColdFire
• Device Core Size: 32b
• Frequency (max): 33.33MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 5V
• Operating Supply Voltage (max): 5.25V
• Operating Supply Voltage (min): 4.75V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Through Hole
• Pin Count: 114
• Package Type: PGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: Compliant

information obtained into memory until all the bytes specified in the coprocessor format
word have been transferred. Following a cpSAVE instruction, the coprocessor should be
in an idle state—that is, not executing any coprocessor instructions.
The cpSAVE instruction is a privileged instruction. When the MC68020/EC020 identifies a
cpSAVE instruction, it checks the S-bit in the SR to determine whether it is operating at
the supervisor privilege level. If the MC68020/EC020 attempts to execute a cpSAVE
instruction while at the user privilege level (S-bit in the SR is clear), it initiates privilege
violation exception processing without accessing any of the CIRs (refer to 7.5.2.3
Privilege Violations).
The MC68020/EC020 initiates format error exception processing if it reads an invalid
format word (or a valid format word whose length field is not a multiple of four bytes) from
the save CIR during the execution of a cpSAVE instruction (refer to 7.2.3.2.3 Invalid
Format Word). The MC68020/EC020 writes an abort mask (refer to 7.2.3.2.3 Invalid
Format Word) to the control CIR to abort the coprocessor instruction prior to beginning
exception processing. Figure 7-16 does not include this case since a coprocessor usually
returns either a not-ready or a valid format code in the context of the cpSAVE instruction.
The coprocessor can return the invalid format word, however, if a cpSAVE is initiated
while the coprocessor is executing a cpSAVE or cpRESTORE instruction and the
coprocessor is unable to support the suspension of these two instructions.
7.2.3.4 COPROCESSOR CONTEXT RESTORE INSTRUCTION. The
coprocessor context restore instruction category includes one instruction. The
coprocessor context restore instruction, denoted by the cpRESTORE mnemonic, forces a
coprocessor to terminate any current operations and to restore a former state. During
execution of a cpRESTORE instruction, the coprocessor can communicate status
information to the main processor by placing format codes in the restore CIR.
7.2.3.4.1 Format. Figure 7-17 shows the format of the cpRESTORE instruction.
The first word of the instruction, the F-line operation word, contains the CpID code in bits
11–9 and an M68000 effective addressing code in bits 5–0. The effective address
encoded in the cpRESTORE instruction is the starting address in memory where the
coprocessor context is stored. The effective address is that of the coprocessor format
word that applies to the context to be restored to the coprocessor.
MOTOROLA
15
1
14
1
13
1
Figure 7-17. Coprocessor Context Restore
12
Freescale Semiconductor, Inc.
1
For More Information On This Product,
Instruction Format (cpRESTORE)
11
EFFECTIVE ADDRESS EXTENSION WORDS (0–5 WORDS)
CpID
Go to: www.freescale.com
M68020 USER’S MANUAL
9
1
8
0
7
6
1
5
EFFECTIVE ADDRESS
0
M68000
7- 23