MPC8572EPXAVND Freescale Semiconductor, MPC8572EPXAVND Datasheet

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... Signal-processing engine (SPE) APU (auxiliary processing unit). Provides an extensive instruction set for vector (64-bit) integer and fractional operations. These instructions use both © 2011 Freescale Semiconductor, Inc. All rights reserved. Document Number: MPC8572EEC 1. Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 2. Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . 10 3. Power Characteristics . . . . . . . . . . . . . . . . . . . . . . . . 15 shows the major 4 ...

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... Twelve local access windows define mapping within local 36-bit address space. — Inbound and outbound ATMUs map to larger external address spaces. – Three inbound windows plus a configuration window on PCI Express MPC8572E PowerQUICC III Integrated Processor Hardware Specifications, Rev Freescale Semiconductor ...

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... Four global high resolution timers/counters per processor that can generate interrupts — Supports a variety of other internal interrupt sources — Supports fully nested interrupt delivery — Interrupts can be routed to external pin for external processing. MPC8572E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 5 Freescale Semiconductor Overview 3 ...

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... Pattern Matching Engine with DEFLATE decompression — Regular expression (regex) pattern matching – Built-in case insensitivity, wildcard support, no pattern explosion – Cross-packet pattern detection MPC8572E PowerQUICC III Integrated Processor Hardware Specifications, Rev and F(p) modes and programmable field size Freescale Semiconductor ...

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... Multiplexed 32-bit address and data bus operating 150 MHz — Eight chip selects support eight external slaves — 8-beat burst transfers — The 32-, 16-, and 8-bit port sizes are controlled by an on-chip memory controller. MPC8572E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 5 Freescale Semiconductor 2 C addressing mode Overview 2 ...

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... CRC generation and verification of inbound/outbound frames — Programmable Ethernet preamble insertion and extraction bytes — MAC address recognition: – Exact match on primary and virtual 48-bit unicast addresses – VRRP and HSRP support for seamless router fail-over MPC8572E PowerQUICC III Integrated Processor Hardware Specifications, Rev Freescale Semiconductor ...

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... Both 1x and 4x LP-serial link interfaces — Long- and short-haul electricals with selectable pre-compensation — Transmission rates of 1.25, 2.5, and 3.125 Gbaud (data rates of 1.0, 2.0, and 2.5 Gbps) per lane MPC8572E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 5 Freescale Semiconductor Overview 7 ...

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... PCI Express 1.0a compatible — Supports x8, x4, x2, and x1 link widths (see following bullet for specific width configuration options) — Auto-detection of number of connected lanes — Selectable operation as root complex or endpoint — Both 32- and 64-bit addressing MPC8572E PowerQUICC III Integrated Processor Hardware Specifications, Rev Freescale Semiconductor ...

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... Supports large block (4-Kbyte) uploads and downloads — Supports continuous bit streaming of entire block for fast upload and download • IEEE Std 1149.1™ compatible, JTAG boundary scan • 1023 FC-PBGA package MPC8572E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 5 Freescale Semiconductor Overview 9 ...

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... DMA Figure 1. MPC8572E Block Diagram MPC8572E e500 Core 32-Kbyte L1 32-Kbyte Instruction L1 Data Cache Cache 1-Mbyte L2 Cache/ SRAM e500 Core 32-Kbyte L1 32-Kbyte Instruction L1 Data Cache Cache PCI Express 4x Serial RapidIO x8/x4/x2/x1 PCI Express External control Controller External control Controller Freescale Semiconductor ...

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... Section 8.2, “FIFO, GMII, MII, TBI, RGMII, RMII, and RTBI AC Timing Specifications,” the recommended operating conditions per protocol. 3. (M,L,O)V may overshoot/undershoot to a voltage and for a maximum duration as shown in IN MPC8572E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 5 Freescale Semiconductor Table 1. Absolute Maximum Ratings Symbol LV DD and eTSEC2) ...

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... V ± 165 mV DD 2.5 V ± 125 mV OV 3.3 V ± 165 3.3 V ± 165 2.5 V ± 125 mV 1.8 V ± GND ± REF DD LV GND GND GND GND ° 105 J and not necessarily the Freescale Semiconductor — 1 — — — — — 2 — 4 — 3 — ...

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... SSTL_1.8 electrical signaling standard for DDR2 or 1.5-V electrical signaling for DDR3. The DDR DQS receivers cannot be operated in single-ended fashion. The complement signal must be properly driven and cannot be grounded. MPC8572E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 5 Freescale Semiconductor + 20 ...

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... and DD_SRDS1 NOTE Supply Notes Voltage L/TV = 2.5/3.3 V — 3.3 V — 3.3 V — 105°C and at GV (min DD_SRDS2 DD DD_SRDS1 is required. If there Freescale Semiconductor and ...

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... This reflects the MPC8572E power dissipation excluding the power dissipation from B/G/L/O/T/XV 2 Typical-65 is based 1 Typical-105 is based 1 Maximum is based 1 MPC8572E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 5 Freescale Semiconductor Table 4. MPC8572E Power Dissipation 2 Typical-65 Typical-105 12.3 12.3 16.3 17 °C, running Dhrystone 105 °C, running Dhrystone 105 °C, running a smoke test. ...

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... G125 Typical Max Unit — 133 MHz — 30.3 ns 1.0 1.2 ns — — +/– 150 ps Section 19.3, “e500 Core PLL Ratio,” . There is CCB Typical Max Unit Notes 125 — MHz 8 — ns Freescale Semiconductor Notes 1 — for ratio — — ...

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... PLL-based devices to track DDRCLK drivers with the specified jitter. 6. For spread spectrum clocking, guidelines are +0% to –1% down spread at a modulation rate between 20 kHz and 60 kHz on DDRCLK. MPC8572E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 5 Freescale Semiconductor /TV of 3.3V ± 2.5V ± 5% (continued) DD ...

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... SYSCLK is the primary clock input for the MPC8572E. 2. Reset assertion timing requirements for DDR3 DRAMs may differ. MPC8572E PowerQUICC III Integrated Processor Hardware Specifications, Rev Min Max Unit μs 100 — 3 — SYSCLKs μs 100 — 4 — SYSCLKs 2 — SYSCLKs — 5 SYSCLKs Freescale Semiconductor Notes 2 1 — ...

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... It is the supply to that far end signal termination is made and is expected equal This rail should track variations in the DC level of MV REF 4. Output leakage is measured with all outputs disabled MPC8572E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 5 Freescale Semiconductor Table 10. PLL Lock Times Symbol Min — 100 — ...

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... MVREF (typ Typical Max 1.575 V 0.51 × – 0.100 V REF μ (typ)=1.8 V and 1 Min Typical Max — 0 25° / OUT DD OUT = 25° / OUT DD OUT n REF Min Max Unit μA — 1500 1250 Freescale Semiconductor Unit 1 2 — — 3 Unit Note 1 ...

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... T is the clock period and abs(tCISKEW) is the absolute value of tCISKEW. MPC8572E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 5 Freescale Semiconductor provide the input AC timing specifications for the DDR controller when of 1.8 V ± 5% ...

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... V ± 5% for DDR2 or 1.5 V ± 5% for DDR3 Symbol Min t 2.5 MCK t DDKHAS 0.917 1.10 1.48 1.95 t DDKHAX 0.917 1.10 1.48 1.95 t DDKHCS 0.917 1.10 1.48 t DISKEW Max Unit Notes — — — — — — — — — — — Freescale Semiconductor ...

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... MHz 667 MHz 533 MHz 400 MHz MDQS preamble start 800 MHz <= 667 MHz MDQS epilogue end 800 MHz MPC8572E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 5 Freescale Semiconductor of 1.8 V ± 5% for DDR2 or 1.5 V ± 5% for DDR3 Symbol Min t 1.95 DDKHCS t DDKHCX 0 ...

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... DDR timing (DD) for the time t DDKHAS NOTE Max Unit Notes 0 for outputs. Output hold time can memory clock reference MCK symbolizes DDR DDKLDX describes the DDR DDKHMH can be DDKHMH follows DDKHMP Table 18 Freescale Semiconductor ...

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... DDR2 and DDR3 SDRAM Interface output timing diagram. MCK[n] MCK[n] ADDR/CMD Write A0 MDQS[n] MDQ[x] Figure 5. DDR2 and DDR3 SDRAM Interface Output Timing Diagram MPC8572E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 5 Freescale Semiconductor tMCK t s DDKHMHmax 0.375 n t DDKHMH(min) = –0 -0.375 ns Figure 4. Timing Diagram for tDDKHMH t ...

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... MPC8572E PowerQUICC III Integrated Processor Hardware Specifications, Rev Ω Ω NOTE Symbol Min V –0 — — IDAC V — JEDEC: 0.5 OHAC V — IXAC V — Max Unit Notes GV + 0.3 V — DD — mV — — mV — — mV — JEDEC 0.6 V — DD — mV — — mV — Freescale Semiconductor ...

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... Input current DD) High-level output voltage (OV = min –2 mA Low-level output voltage (OV = min mA Note: 1. The symbol this case, represents the OV IN MPC8572E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 5 Freescale Semiconductor Symbol Min V — — — IDAC V — — OHAC V — IXAC V — MP Symbol ...

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... MPC8572E PowerQUICC III Integrated Processor Hardware Specifications, Rev Table 22. DUART AC Timing Specifications of 3.3V ± 5 sampled 0 after the 1-to-0 transition of the start bit. Subsequent bit values are Section 8.3, “SGMII Interface Electrical Value Unit f /1,048,576 baud CCB f /16 baud CCB 16 — Section 9, “Ethernet Management Freescale Semiconductor Notes ...

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... Min, IOH = –1.0 mA Output low voltage (LV /TV = Min 1.0 mA Input high voltage Input low voltage MPC8572E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 5 Freescale Semiconductor Table 24. The RGMII and RTBI signals are based on a 2.5-V CMOS Symbol Min Max LV 3.13 3. VOH 2.40 ...

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... MPC8572E PowerQUICC III Integrated Processor Hardware Specifications, Rev Symbol Min I — –15 IL and TV symbols referenced /TV of 2.5V ± Symbol t FIT t /t FITH FIT t FITJ Max Unit Notes 1, 2,3 μA 10 μA — Table 1. Min Typ Max 5.3 8.0 100 — — 250 Freescale Semiconductor 3 Unit ...

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... FIFO mode under operation. Refer to Restrictions,” for more detailed description. Figure 7 and Figure 8 show the FIFO timing diagrams. GTX_CLK t FITH TXD[7:0] TX_EN TX_ER MPC8572E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 5 Freescale Semiconductor /TV of 2.5V ± Symbol t FITR t FITF t FITDV t ...

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... GTKHDX represents the GMII(G) transmit (TX) clock. For rise and fall times, GTX t FIRR t FIRF 1 Min Typ Max 2.5 — — 0.5 — 5.0 2 — — 1.0 2 — — 1.0 symbolizes GMII GTKHDV symbolizes GMII transmit timing (GT) with respect Freescale Semiconductor Unit ...

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... Note that, in general, the clock reference symbol representation is based on three letters representing the clock of a particular functional. For example, the subscript of t convention is used with the appropriate letter: R (rise (fall). 2. Guaranteed by design. Figure 10 provides the AC test load for eTSEC. Output MPC8572E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 5 Freescale Semiconductor t GTX t t GTXH GTXF t ...

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... Note that, in represents the MII(M) transmit (TX) clock. For rise and fall times, the latter MTX t GRXR Min Typ Max — 400 — — 40 — 35 — 1.0 — 4.0 1.0 — 4.0 symbolizes MII MTKHDX Freescale Semiconductor Unit ...

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... MII (M) receive (RX) clock. For rise and fall times, the latter convention is used MRX with the appropriate letter: R (rise (fall). 2. Guaranteed by design. Figure 13 provides the AC test load for eTSEC. Output MPC8572E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 5 Freescale Semiconductor t MTX t t MTXH MTXF t MTKHDX Figure 12 ...

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... For example, (K) going high (H) until the TTX symbolizes the TBI transmit timing TTKHDX represents the TBI (T) transmit TTX Freescale Semiconductor Unit ...

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... R (rise (fall). For symbols representing skews, the subscript is skew (SK) followed by the clock that is being skewed (TRX). 2. Guaranteed by design. 3. The signals “TBI Receive Clock 0” and “TBI Receive Clock 1” refer to TSECn_RX_CLK and TSECn_TX_CLK pins respectively. These two clock signals are also referred as PMA_RX_CLK[0:1]. MPC8572E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 5 Freescale Semiconductor t TTX t TTXH ...

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... DD DD Symbol t TRRX t /t TRRH TRRX t TRRJ t TRRR t TRRF t TRRDVKH t TRRDXKH t TRXR Valid Data t TRDXKH t TRDXKH t TRDVKH Table 33. Min Typ Max 7.5 8.0 8 — — 250 — — 1.0 — — 1.0 2.0 — — 1.0 — — Freescale Semiconductor Unit ...

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... Duty cycle may be stretched/shrunk during speed changes or while transitioning to a received packet's clock domains as long as the minimum duty cycle is not violated and stretching occurs for no more than three t between. MPC8572E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 5 Freescale Semiconductor t TRR valid data ...

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... TXD[4] TXEN TXERR RXD[8:5] RXD[3:0] RXD[7:4] t SKRGT RXD[4] RXD[9] RXDV RXERR /TV of 2.5/ 3.3 V ± 5 Symbol Min t 15.0 RMT t RMTH t RMTJ t 1.0 RMTR t 1.0 RMTF t RGT t SKRGT t SKRGT Typ Max 20.0 25 — — 250 — 2.0 — 2.0 Freescale Semiconductor Unit ...

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... TSECn_TX_CLK duty cycle TSECn_TX_CLK peak-to-peak jitter Rise time TSECn_TX_CLK (20%–80%) Fall time TSECn_TX_CLK (80%–20%) RXD[1:0], CRS_DV, RX_ER setup time to TSECn_TX_CLK rising edge MPC8572E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 5 Freescale Semiconductor Ethernet: Enhanced Three-Speed Ethernet (eTSEC) /TV of 2.5/ 3.3 V ± 5 ...

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... RMRDV Figure 21. RMII Receive AC Timing Diagram 22, where C is the external (on board) AC-Coupled capacitor. Each TX as long as such termination does not violate Min Typ Max 2.0 — — symbolizes MII receive MRDVKH clock reference (K) MRX Ω RMRR t RMRDX Figure 54. Freescale Semiconductor Unit ns ...

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... Phase jitter. Deviation in edge location with respect to mean edge REFPJ location Note applies only when 125 MHz SerDes2 reference clock frequency is selected through cfg_srds_sgmii_refclk during POR. MPC8572E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 5 Freescale Semiconductor Ethernet: Enhanced Three-Speed Ethernet (eTSEC) Min Typical Max Units — ...

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... Freescale Semiconductor Notes — — Equalization setting: 1.0x Equalization setting: 1.09x Equalization setting: 1.2x Equalization setting: 1.33x Equalization setting: 1.5x Equalization setting: 1.71x Equalization setting: 2. — — — ...

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... SerDes2 transmitter is terminated with 100-Ω differential load between SD2_TX[n] and OS SD2_TX[n]. 50 Ω Transmitter 50 Ω MPC8572E SGMII SerDes Interface 50 Ω Receiver 50 Ω Figure 22. 4-Wire AC-Coupled SGMII Serial Link Connection Example MPC8572E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 5 Freescale Semiconductor Symbol Min Δ V — — =1.1 V. ...

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... DD_SRDS2 — N/A V 100 — RX_DIFFp-p 175 — VLOS 30 — 65 — V — CM_ACp 100 RX_DIFF Z 20 — RX_CM V — xcorevss Max Unit Notes 1.155 V — — 1 1200 100 175 100 mV 5 Ω 120 — Ω 35 — — Freescale Semiconductor ...

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... The external AC coupling capacitor is required recommended to be placed near the device transmitter outputs. 4. See RapidIO 1x/4x LP Serial Physical Layer Specification for interpretation of jitter specifications. MPC8572E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 5 Freescale Semiconductor Ethernet: Enhanced Three-Speed Ethernet (eTSEC) Figure 25, respectively. ...

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... Ethernet: Enhanced Three-Speed Ethernet (eTSEC RX_DIFFp-p-max V /2 RX_DIFFp-p-min 0 − RX_DIFFp-p-min − RX_DIFFp-p-max 0 Figure 24. SGMII Receiver Input Compliance Mask Figure 25. SGMII AC Test/Measurement Load MPC8572E PowerQUICC III Integrated Processor Hardware Specifications, Rev 0.275 0.4 0.6 Time (UI) 1 0.725 Freescale Semiconductor ...

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... Parameter/Condition TSEC_1588_CLK clock period TSEC_1588_CLK duty cycle TSEC_1588_CLK peak-to-peak jitter Rise time eTSEC_1588_CLK (20%–80%) Fall time eTSEC_1588_CLK (80%–20%) TSEC_1588_CLK_OUT clock period MPC8572E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 5 Freescale Semiconductor Ethernet: Enhanced Three-Speed Ethernet (eTSEC) t T1588CLKOUT t T1588CLKOUTH t T1588OV is non-inverting. Otherwise count starting falling edge. ...

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... Typ Max Unit — 3.0 ns — — the maximum clock period TX_CLK is defined in terms of T1588CLK “Section 8, “Ethernet: Enhanced Table 43 and Table 44. /TV =3 Max Unit Notes 3. 0.3 V — DD 0.50 V — — V — 0.90 V — μA 40 — Freescale Semiconductor Note — — 2 T1588CLK ...

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... Table 45. MII Management AC Timing Specifications At recommended operating conditions with LV Parameter/Condition ECn_MDC frequency ECn_MDC period ECn_MDC clock pulse width high ECn_MDC to ECn_MDIO delay ECn_MDIO to ECn_MDC setup time MPC8572E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 5 Freescale Semiconductor Ethernet Management Interface Electrical Characteristics Symbol Min I –600 ...

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... MDDXKH t MDKHDX Typ Max Unit — — ns — — (first two letters of functional block)(signal)(state) for outputs. For example The actual CCB = 533/(2*4*8) = 533/64 = 8.3 MHz. MDC /448. Refer to MPC8572E reference manual’s t MDCR Freescale Semiconductor Notes — MDKHDX ...

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... Input current 1 ( High-level output voltage (BV = min –1 mA Low-level output voltage (BV = min mA Note: 1. The symbol this case, represents the BV IN MPC8572E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 5 Freescale Semiconductor Symbol Min BV 3. –0 — – 0 — this case, represents the BV symbol referenced in ...

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... TBD — V — V 0.2 V 0.45 V Table 1. = 3 3.3 V DC)—PLL Enabled DD Min Max Unit Notes 6. — 150 ps 1.8 — ns 1.7 — ns 1.0 — ns 1.0 — ns 1.5 — ns — 2.3 ns — 2.4 ns — 2.3 ns — 2.3 ns Freescale Semiconductor = 1 — 7 — ...

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... LGTA/LUPWAIT input hold from local bus clock LALE output negation to high impedance for LAD/LDP (LATCH hold time) Local bus clock to output valid (except LAD/LDP and LALE) MPC8572E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 5 Freescale Semiconductor = 3.3 V DC)—PLL Enabled (continued 3.3 V ± 5%. (continued) DD Symbol ...

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... For example, clock LBK symbolizes local bus timing (LB) for the LBOTOT = 1 1.8 V DC)—PLL Enabled DD Min Max Unit Notes 6. — — 150 2.4 — 1.9 — 1.1 — 1.1 — 1.2 — ns Freescale Semiconductor ...

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... Maximum possible clock skew between a clock LCLK[m] and a relative clock LCLK[n]. Skew measured between complementary signals Guaranteed by design. Figure 29 provides the AC test load for the local bus. Output MPC8572E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 5 Freescale Semiconductor = 1.8 V DC)—PLL Enabled (continued 1.8 V ± 5% (continued Symbol ...

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... LBKHOZ2 t t LBKHOV3 LBKHOX2 t LBOTOT t LBKHOV4 of 3.3 V ± Symbol Min t 12 LBK LBKH/ LBK t 2.3 LBKHKT t 5.8 LBIVKH1 t 5.7 LBIVKL2 t -1.3 LBIXKH1 t -1.3 LBIXKL2 t LBIXKH1 t LBIXKH2 = 3 with PLL DD Max Unit Notes — — 4.0 ns — — — — — Freescale Semiconductor ...

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... LGTA/LUPWAIT (which is captured on the rising edge of the internal clock). MPC8572E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 5 Freescale Semiconductor of 3.3 V ± Symbol ...

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... Output (Data) Signals: LAD[0:31]/LDP[0:3] Output (Address) Signal: LAD[0:31] LALE Figure 31. Local Bus Signals (PLL Bypass Mode) MPC8572E PowerQUICC III Integrated Processor Hardware Specifications, Rev LBKHKT t LBIVKH1 t LBKLOV1 t LBKLOX1 t LBKLOV2 t t LBKLOX2 LBKLOV3 t t LBKLOV4 LBOTOT t LBIXKH1 t LBIVKL2 t LBIXKL2 t LBKLOZ1 t LBKLOZ2 Freescale Semiconductor ...

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... UPM Mode Input Signal: LUPWAIT Input Signals: LAD[0:31]/LDP[0:3] UPM Mode Output Signals: LCS[0:7]/LBS[0:3]/LGPL[0:5] Figure 32. Local Bus Signals, GPCM/UPM Signals for LCCR[CLKDIV (PLL Enabled) MPC8572E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 5 Freescale Semiconductor t t LBKHOZ1 LBKHOV1 t LBIVKH2 t LBIVKH1 ...

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... UPM Mode Input Signal: LUPWAIT Input Signals: LAD[0:31]/LDP[0:3] UPM Mode Output Signals: LCS[0:7]/LBS[0:3]/LGPL[0:5] Figure 33. Local Bus Signals, GPCM/UPM Signals for LCCR[CLKDIV (PLL Bypass Mode) MPC8572E PowerQUICC III Integrated Processor Hardware Specifications, Rev LBKLOX1 LBKLOV1 t LBIVKH1 t LBKLOZ1 t LBIVKL2 t LBIXKL2 t LBIXKH1 Freescale Semiconductor ...

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... UPM Mode Input Signal: LUPWAIT Input Signals: LAD[0:31]/LDP[0:3] UPM Mode Output Signals: LCS[0:7]/LBS[0:3]/LGPL[0:5] Figure 34. Local Bus Signals, GPCM/UPM Signals for LCCR[CLKDIV (PLL Enabled) MPC8572E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 5 Freescale Semiconductor t t LBKHOV1 LBKHOZ1 t LBIVKH2 t LBIVKH1 ...

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... UPM Mode Input Signal: LUPWAIT Input Signals: LAD[0:31]/LDP[0:3] UPM Mode Output Signals: LCS[0:7]/LBS[0:3]/LGPL[0:5] Figure 35. Local Bus Signals, GPCM/UPM Signals for LCCR[CLKDIV (PLL Bypass Mode) MPC8572E PowerQUICC III Integrated Processor Hardware Specifications, Rev LBKLOX1 LBKLOV1 t LBIVKH1 t LBKLOZ1 t LBIVKL2 t LBIXKL2 t LBIXKH1 Freescale Semiconductor ...

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... JTAG external clock rise and fall times TRST assert time Input setup times: Boundary-scan data Input hold times: Boundary-scan data Valid times: Boundary-scan data Output hold times: Boundary-scan data MPC8572E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 5 Freescale Semiconductor of 3.3 V ± 5 Symbol Min f 0 JTG t 30 ...

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... Note that, in general, the clock JTG . TCLK . TCLK = 50 Ω JTKHKL t JTG VM = Midpoint Voltage ( TRST VM = Midpoint Voltage (OV DD /2) Figure 38. TRST Timing Diagram 1 (continued) Max Unit the midpoint of the signal in question. TCLK Figure 36). symbolizes JTAG JTDVKH clock reference JTG Ω JTGR t JTGF VM Freescale Semiconductor Notes 5, 6 ...

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... Output voltage (open drain or open collector) condition = 3 mA sink current. 2. Refer to the MPC8572E PowerQUICC™ III Integrated Host Processor Family Reference Manual for information on the digital filter used. 3. I/O pins will obstruct the SDA and SCL lines if OV MPC8572E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 5 Freescale Semiconductor VM t JTDVKH t ...

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... OV — DD 0.2 × OV — DD — 400 2 symbolizes I C timing (I2) I2DVKH clock reference (K) going to the high I2C symbolizes I I2PVKH ) of the SCL signal. I2CL Freescale Semiconductor Unit 4 kHz μs μs μs μs ns μs μs μs μ for 2 C clock ...

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... Input current 1 ( High-level output voltage (BV = min –2 mA Low-level output voltage (BV = min mA Note: 1. Note that the symbol BV IN MPC8572E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 5 Freescale Semiconductor Ω Figure 40 Test Load 2 C bus. t I2DVKH t I2SXKL t t I2CH I2SVKH t I2DXKL Sr 2 Figure 41. I ...

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... GND – 0.3 OL symbol referenced in IN Symbol Min –0 TBD – 0 – 0. — — OL symbol referenced 2.5 V DC. DD Max Unit 2. 0 0.7 V μA 10 – 0 0.4 V Table 1. = 1.8 V DC. DD Max Unit μA TBD — V — V 0.2 V 0.45 V Table 1. Freescale Semiconductor ...

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... The transmitter output signals and the receiver input signals SDn_TX, SDn_TX, SDn_RX and SDn_RX each have a peak-to-peak swing Volts. This is also referred as each signal wire’s Single-Ended Swing. MPC8572E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 5 Freescale Semiconductor Symbol t PIWID PIWID = 50 Ω ...

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... B| Volts. DIFFp DIFFp |(A – B)| Volts, which is twice of differential DIFFp-p DIFFp = 2*|V TX-DIFFp-p OD Figure defined as the difference of OD The V value can be either positive defined as the difference of the ID The V value can be either positive example for differential waveform. cm_out Freescale Semiconductor = ...

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... The SDn_REF_CLK and SDn_REF_CLK are internally AC-coupled differential inputs as shown in Figure 44. Each differential clock input (SDn_REF_CLK or SDn_REF_CLK) has on-chip 50-Ω termination to SGND_SRDSn (xcorevss) followed by on-chip AC-coupling. MPC8572E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 5 Freescale Semiconductor Differential Swing Differential Peak Voltage, V ...

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... Differential Mode — The input amplitude of the differential clock must be between 400mV and 1600mV differential peak-peak (or between 200mV and 800mV differential peak). In other words, each signal wire MPC8572E PowerQUICC III Integrated Processor Hardware Specifications, Rev Ω Input Amp 50 Ω Freescale Semiconductor ...

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... Input Amplitude or Differential Peak < 800 _REF_CLK SD n _REF_CLK Figure 45. Differential Reference Clock Input DC Requirements (External DC-Coupled) MPC8572E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 5 Freescale Semiconductor High-Speed Serial Interfaces (HSSI) Section 15.2.1, “SerDes Reference Figure 46 shows the SerDes reference clock ...

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... LVPECL outputs can produce signal with too large amplitude and may need to be DC-biased at clock driver output first, then followed with series attenuation resistor to reduce the amplitude, additionally to AC-coupling. MPC8572E PowerQUICC III Integrated Processor Hardware Specifications, Rev < < _REF_CLK Input Amplitude < Vmax Vcm + 400 mV Vcm > Vmin Vcm – 400 mV 800 Freescale Semiconductor ...

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... They might also vary from one vendor to the other. Therefore, Freescale Semiconductor can neither provide the optimal clock driver reference circuits, nor guarantee the correctness of the following clock driver connection reference circuits. The system designer is recommended ...

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... For example, if the LVPECL output’s differential peak is 900mV and the desired SerDes reference clock input amplitude is selected as 600mV, the attenuation factor is 0.67, which requires R2 = 25Ω. Consult MPC8572E PowerQUICC III Integrated Processor Hardware Specifications, Rev _REF_CLK 100 Ω differential PWB trace SD n _REF_CLK MPC8572E 50 Ω SerDes Refer. CLK Receiver 50 Ω Figure 50 Freescale Semiconductor ...

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... Phase noise less than 100KHz can be tracked by the PLL and data recovery loops and is less of a problem. Phase noise above 15MHz is filtered by the PLL. The most problematic phase noise MPC8572E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 5 Freescale Semiconductor SD n _REF_CLK 10nF ...

Page 80

... MPC8572E PowerQUICC III Integrated Processor Hardware Specifications, Rev 1.1V ± 5%. DD_SRDS1 DD_SRDS2 Symbol Rise Edge Rate Fall Edge Rate Rise-Fall Matching Figure 52. Figure 53 _REF_CLK SD n _REF_CLK Min Max Unit Notes 1.0 4.0 V/ 1.0 4.0 V/ +200 mV 2 — -200 mV 2 — Fall Edge Rate Freescale Semiconductor ...

Page 81

... Note that external AC Coupling capacitor is required for the above three serial transmission protocols with the capacitor value defined in specification of each protocol section. 16 PCI Express This section describes the DC and AC electrical specifications for the PCI Express bus of the MPC8572E. MPC8572E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 5 Freescale Semiconductor SD1_RX n or SD1_TX n or SD2_RX n SD2_TX n ...

Page 82

... Each UI is 400 ps ± 300 ppm. UI does not account for Spread Spectrum Clock dictated variations. See Note 1. 0.8 — 1 TX-DIFFp-p Min Typical Max Units Notes — 10 — — — 100 ps — –50 — — Comments = 2*| See Note 2. TX-D+ TX-D- Freescale Semiconductor ...

Page 83

... Voltage I TX Short Circuit TX-SHORT Current Limit T Minimum time TX-IDLE-MIN spent in Electrical Idle MPC8572E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 5 Freescale Semiconductor Min Nominal Max Units –3.0 –3.5 -4.0 dB Ratio of the V bits after a transition divided by the V the first bit after a transition. See Note 2. ...

Page 84

... Downstream and one Upstream Port. See Note 7. TX-EYE-MEDIAN-to-MAX-JITTER built-in. An external AC Coupling capacitor is required. TX Comments Figure 57 and measured over Figure 55.) = 0.30 UI for the TX-JITTER-MAX median is less than half of the total Figure 57). Note that the series Figure 57 for both V and V . TX-D+ TX-D- Freescale Semiconductor ...

Page 85

... RX-DIFF (D+ D– Crossing Point) Figure 55. Minimum Transmitter Timing and Voltage Output Compliance Specifications MPC8572E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 5 Freescale Semiconductor is specified using the passive compliance/test measurement load (see NOTE [Transition Bit 800 mV TX-DIFFp-p-MIN [De-Emphasized Bit] 566 > ...

Page 86

... D+ and D- lines biased See Note Differential mode impedance. See Note 5 Required well Impedance (50 ± 20% tolerance). See Notes 2 and 5. Required well Impedance when the Receiver terminations do not have power. See Note 2*|V -V RX-IDLE-DET-DIFFp-p RX-D+ RX-D- Measured at the package pins of the Receiver Freescale Semiconductor |/2 | ...

Page 87

... It is recommended that the recovered calculated using all edges in the 3500 consecutive UI interval with a fit algorithm using a minimization merit function. Least squares and median deviation fits have worked well with experimental and simulated data. MPC8572E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 5 Freescale Semiconductor Min Nominal Max Units — ...

Page 88

... Figure 56. Minimum Receiver Eye Timing and Voltage Compliance Specification MPC8572E PowerQUICC III Integrated Processor Hardware Specifications, Rev specified using the passive compliance/test measurement load (see NOTE Figure 57). Note that the series capacitors, CTX, are V > 175 mV RX-DIFFp-p-MIN 0 RX-EYE-MIN RX-DIFF (D+ D– Crossing Point) Freescale Semiconductor ...

Page 89

... All unit intervals are specified with a tolerance of +/– 100 ppm. The worst case frequency difference between any transmit and receive clock is 200 ppm. To ensure interoperability between drivers and receivers of different vendors and technologies, AC coupling at the receiver input must be used. MPC8572E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 5 Freescale Semiconductor NOTE Pin Pin ...

Page 90

... XAUI, suitably modified for applications at the baud intervals and reaches described herein. MPC8572E PowerQUICC III Integrated Processor Hardware Specifications, Rev Min Typical Max Units — 10(8) — applies only to serial RapidIO with 125-MHz reference clock — — –40 — Section 8.1, “Enhanced Three-Speed Comments — — Freescale Semiconductor ...

Page 91

... Total Jitter Multiple output skew Unit Interval Table 66. Short Run Transmitter AC Timing Specifications—2.5 GBaud Characteristic Output Voltage, Differential Output Voltage Deterministic Jitter Total Jitter MPC8572E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 5 Freescale Semiconductor Range Symbol Min Max V –0.40 2. 500 ...

Page 92

... Skew at the transmitter output between lanes of a multilane link ps +/– 100 ppm Unit Notes Volts Voltage relative to COMMON of either signal comprising a differential pair mV p-p — UI p-p — UI p-p — ps Skew at the transmitter output between lanes of a multilane link ps +/- 100 ppm Freescale Semiconductor ...

Page 93

... The output eye pattern of an LP-Serial transmitter that implements pre-emphasis (to equalize the link and reduce inter-symbol interference) need only comply with the Transmitter Output Compliance Mask when pre-emphasis is disabled or minimized. MPC8572E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 5 Freescale Semiconductor Range Symbol Min ...

Page 94

... MPC8572E PowerQUICC III Integrated Processor Hardware Specifications, Rev Time min (mV) V max (mV) DIFF DIFF 250 500 400 800 250 500 400 800 250 500 400 800 1-B 1-A A (UI) B (UI) 0.175 0.39 0.175 0.39 0.175 0.39 0.175 0.39 0.175 0.39 0.175 0.39 Freescale Semiconductor 1 ...

Page 95

... Total jitter is composed of three components, deterministic jitter, random jitter and single frequency sinusoidal jitter. The sinusoidal jitter may have any amplitude and frequency in the unshaded region of is included to ensure margin for low frequency jitter, wander, noise, crosstalk and other variable system effects. MPC8572E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 5 Freescale Semiconductor Range Symbol Min ...

Page 96

... UI 320 320 Frequency Unit Notes mV p-p Measured at receiver UI p-p Measured at receiver UI p-p Measured at receiver UI p-p Measured at receiver ns Skew at the receiver input between lanes of a multilane link — — ps +/- 100 ppm Figure 59. The sinusoidal jitter component 1.875 MHz 20 MHz Freescale Semiconductor ...

Page 97

... Because the LP-Serial electrical specification are guided by the XAUI electrical interface specified in Clause 47 of IEEE 802.3ae-2002, the measurement and test requirements defined here are similarly guided by Clause 47. Additionally, the CJPAT test pattern defined in Annex 48A of IEEE 802.3ae-2002 is MPC8572E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 5 Freescale Semiconductor (Table 72, Table ...

Page 98

... MPC8572E PowerQUICC III Integrated Processor Hardware Specifications, Rev Figure 60 and Table 75. Note that for this to occur, the test signal must Section 17.6, “Receiver Section 17.6, “Receiver Specifications,” Specifications,” is Freescale Semiconductor -12 . ...

Page 99

... The package parameters are as provided in the following list. The package type × 33 mm, 1023 flip chip plastic ball grid array (FC-PBGA). Package outline Interconnects Ball Pitch Ball Diameter (Typical) Solder Balls Solder Balls (Lead-Free) MPC8572E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 5 Freescale Semiconductor 33 mm × 1023 1 mm 0.6 mm 63% Sn 37% Pb 96.5% Sn 3.5% Ag ...

Page 100

... All dimensions are symmetric across the package center lines unless dimensioned otherwise. 4. Maximum solder ball diameter measured parallel to datum A. 5. Datum A, the seating plane, is determined by the spherical crowns of the solder balls. MPC8572E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 5 100 Freescale Semiconductor ...

Page 101

... D1_MBA[0:2] Bank Select D1_MWE Write Enable D1_MCAS Column Address Strobe MPC8572E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 5 Freescale Semiconductor Table 76. MPC8572E Pinout Listing Signal Name Package Pin Number DDR SDRAM Memory Interface 1 D15, A14, B12, D12, A15, B15, B13, C13, ...

Page 102

... AE6, AK2, AJ6, K6 W1, U4, U3, T1, T2, T3, R1, R2, T5, R4, Y3, P1, N2, AF1, M2, M1 Y1, W3, P3 AA2 Power Pin Type Notes Supply O GV — — — — — I/O GV — DD I/O GV — — — — DD I/O GV — DD I/O GV — — — — DD Freescale Semiconductor ...

Page 103

... LGPL0/LFCLE UPM General Purpose Line 0 / Flash Command Latch Enable LGPL1/LFALE UPM General Purpose Line 1/ Flash Address Latch Enable MPC8572E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 5 Freescale Semiconductor Signal Name Package Pin Number AD1 AA1 L3, L1, K1, K2 AB1, AG2, AC1, AH2 ...

Page 104

... AA25 M28 L28 T24, R24, R25, R27, R28, AB27, AB28, P27, R30, AC28, R29, T31 U24 1588 AM22 AM23 Power Pin Type Notes Supply I/O BV — — — — — — — — — — — — — — DD Freescale Semiconductor ...

Page 105

... TSEC1_RX_DV/FIFO1_RX_DV Receive Data Valid /FIFO1_RXC[0] TSEC1_RX_ER/FIFO1_RX_E Receive Data Error R/FIFO1_RXC[1] TSEC1_TX_CLK/FIFO1_TX_C Transmit Clock In LK MPC8572E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 5 Freescale Semiconductor Signal Name Package Pin Number AA23 AC23 AA22 AB23 Ethernet Management Interface 1 AL30 AM25 Ethernet Management Interface 3 ...

Page 106

... AJ21, AK20 AH21, AF20, AC17, AF21, AD18, AF22, AE20, AB18 AE19 AJ20 AE18 AL23 AJ22 AD19 AC19 AB19 AB17 Three-Speed Ethernet Controller 3 AG18, AG17, AH17, AH19 AG16, AK19, AD16, AJ19 AE17 AF17 AG14 AH15 Power Pin Type Notes Supply I — Freescale Semiconductor ...

Page 107

... Receive Data (positive) SD1_RX[7:0] Receive Data (negative) SD1_TX[7] PCIe1 Tx Data Lane 7 / SRIO or PCIe2 Tx Data Lane 3 / PCIe3 TX Data Lane 1 MPC8572E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 5 Freescale Semiconductor Signal Name Package Pin Number AF16 AJ18 Three-Speed Ethernet Controller 4 AD15, AC16, AC14, AB16 ...

Page 108

... DD_SR DS1 DD_SR DS1 I XV — DD_SR DS1 I XV — DD_SR DS1 — — 26 — — 27 — — 28 — — — DD_SR DS2 I XV — DD_SR DS2 O XV — DD_SR DS2 O XV — DD_SR DS2 O XV — DD_SR DS2 Freescale Semiconductor ...

Page 109

... Memory Debug Source Port ID MDVAL Memory Debug Data Valid CLK_OUT Clock Out RTC Real Time Clock SYSCLK System Clock MPC8572E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 5 Freescale Semiconductor Signal Name Package Pin Number AD26 AH27, AG25, AE25, AD27 AH32 AG32 AG31 — ...

Page 110

... TEST_SEL Test Select 0 ASLEEP Asleep MPC8572E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 5 110 Signal Name Package Pin Number AA29 JTAG T28 T27 T26 U26 AA32 DFT V32 V31 N24 K28 Power Management P28 Power Pin Type Notes Supply 15 Freescale Semiconductor ...

Page 111

... SerDes Transceiver Pad GND (xpadvss) XGND_SRDS2 SerDes Transceiver Pad GND (xpadvss) MPC8572E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 5 Freescale Semiconductor Signal Name Package Pin Number Power and Ground Signals A18, A25, A29, C3, C6, C9, C12, C15, C20, C22, E5, E8, E11, E14, ...

Page 112

... D21, F18, G20, H17, J22, K15, K20 Power Pin Type Notes Supply — — — — — — — — — — — — — OVDD — — LVDD — — TVDD — — GVDD — — BVDD — Freescale Semiconductor ...

Page 113

... SSTL_1.8 Reference Voltage MVREF2 SSTL_1.8 Reference Voltage SD1_IMP_CAL_RX SerDes1 Rx Impedance Calibration MPC8572E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 5 Freescale Semiconductor Signal Name Package Pin Number L14, M13, M15, M17, N12, N14, N16, N20, N22, P11, P13, P15, P17, P19, P21, P23, ...

Page 114

... Package Pin Number T32 AC32 AM32 AA31 AB31 Power Pin Type Notes Supply I 100Ω — (±1%) to GND O AVDD_S 17 RDS analog I 200Ω — (±1%) to GND I 100Ω — (±1%) to GND O AVDD_S 17 RDS analog — internal 14 diode — internal 14 diode Freescale Semiconductor ...

Page 115

... This pin is only an output in eTSEC3 FIFO mode when used as Rx flow control. 24. TSEC2_TXD[1] is used as cfg_dram_type. IT MUST BE VALID AT POWER-UP, EVEN BEFORE HRESET ASSERTION. MPC8572E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 5 Freescale Semiconductor Signal Name Package Pin Number A16, A20, B16, B17, ...

Page 116

... These pins should be pulled to ground (GND). 34. These pins are sampled at POR for General Purpose configuration use by software. Their value has no impact on the functionality of the hardware. MPC8572E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 5 116 Signal Name Package Pin Number Power Pin Type Notes Supply Freescale Semiconductor ...

Page 117

... Ratio.” The memory bus clock speed must be less than or equal to the CCB clock rate which in turn must be less than the DDR data rate. MPC8572E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 5 Freescale Semiconductor Maximum Processor Core Frequency 1067 MHz 1200 MHz ...

Page 118

... Table 81; Table 82. Note that in asynchronous mode, the DDR data rate Table 79. CCB Clock Ratio Binary Value of CCB:SYSCLK Ratio LA[29:31] Signals 000 4:1 001 5:1 010 6:1 011 8:1 100 10:1 101 12:1 110 Reserved 111 Reserved Table 79; Table 79: Freescale Semiconductor ...

Page 119

... In asynchronous mode, the DDR PLL rate to DDRCLK ratios listed in to DDRCLK ratio, because the DDR PLL rate in asynchronous mode means the DDR data rate resulting from DDR PLL output. MPC8572E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 5 Freescale Semiconductor Table 80. e500 Core0 to CCB Clock Ratio Binary Value of LBCTL, LALE, ...

Page 120

... SYSCLK (MHz) 41.66 50 66.66 Platform /CCB Frequency (MHz) 415 400 498 400 533 417 500 500 600 3:1 4:1 6:1 8:1 10:1 12:1 14:1 Synchronous mode 83 100 111 133.33 400 444 533 500 555 600 Freescale Semiconductor ...

Page 121

... Newton). Rating Junction to ambient, natural convection Junction to ambient, natural convection Junction to ambient (at 200 ft./min.) Junction to ambient (ar 200 ft./min.) Junction to board MPC8572E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 5 Freescale Semiconductor × ( 527 MHz PCI Express link width ---------------------------------------------------------------------------------------------- × ...

Page 122

... Ideality factor is defined as the deviation from the ideal diode equation: qV ___ f nKT – Another useful equation is – Where Forward current Saturation current Voltage at diode d MPC8572E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 5 122 Board Symbol Value — R 0.5 ΘJC Freescale Semiconductor Unit Notes ° C/W 5 ...

Page 123

... The PLL for the SerDes1 module is used for PCI Express and Serial Rapid IO interfaces. • The PLL for the SerDes2 module is used for the SGMII interface. MPC8572E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 5 Freescale Semiconductor is flowing H is flowing L –19 C) – ...

Page 124

... DD 10 Ω 2.2 µF 2.2 µF Low ESL Surface Mount Capacitors GND Figure 62. PLL Power Supply Filter Circuit NOTE _LBIU, AV _SRDS1 and and preferably these DD Figure 62, one to each of the pin being supplied to minimize trace DD filter DD and DD Freescale Semiconductor DD ...

Page 125

... Only surface mount technology (SMT) capacitors should be used to minimize inductance. Connections from all capacitors to power and ground should be done with multiple vias to further reduce inductance. MPC8572E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 5 Freescale Semiconductor 1.0 Ω 1 2.2 µF 2.2 µ ...

Page 126

... other in value. Then MPC8572E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 5 126 DD C). is trimmed until the voltage at the pad equals P P )/2. N _SRDSn and DD (see Figure 64). The DD and R are designed to be close to each N Freescale Semiconductor , ...

Page 127

... MPC8572E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 5 Freescale Semiconductor Pad Data R P OGND Figure 64. Driver Impedance Measurement System Design Information DD SW2 SW1 127 ...

Page 128

... MPC8572E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 5 128 Table 85. Impedance Characteristics Management 45 Target 18 Target (full strength mode) 36 Target (half strength mode) 45 Target 18 Target (full strength mode) 36 Target (half strength mode) Table 105°C. j DDR DRAM Symbol Freescale Semiconductor , DD Unit Ω Ω ...

Page 129

... JTAG interface may need to be wired onto the system in future debug situations. • No pull-up/pull-down is required for TDI, TMS, TDO or TCK. MPC8572E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 5 Freescale Semiconductor allows the COP port to independently assert HRESET or TRST, Figure 65, for connection to the target system, and is ...

Page 130

... System Design Information COP_SRESET COP_HRESET COP_CHKSTP_OUT MPC8572E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 5 130 COP_TDO NC COP_TDI 3 4 COP_TRST COP_VDD_SENSE COP_TCK 7 8 COP_CHKSTP_IN COP_TMS KEY 13 No pin GND 15 16 Figure 65. COP Connector Physical Pinout Freescale Semiconductor ...

Page 131

... BSDL testing. The switch should be closed to position A during BSDL testing to avoid accidentally asserting the TRST line. If BSDL testing is not being performed, this switch should be closed to position B. 6. Asserting SRESET causes a machine check interrupt to the e500 cores. MPC8572E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 5 Freescale Semiconductor COP_HRESET COP_SRESET B A ...

Page 132

... If the high-speed SerDes 2 interface (SGMII) is not used at all, the unused pin should be terminated as described in this section. The following pins must be left unconnected (float): MPC8572E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 5 132 _SRDS1. Pins K31 and C30 must be tied to XGND_SRDS1 DD _SRDS1. Pins K31 and C30 must be tied to XGND_SRDS1 DD Freescale Semiconductor ...

Page 133

... I/O pins should be terminated as described in this section. The following pins must be left unconnected (float): • SD2_TX[3:0] • SD2_TX[3:0] • Reserved pins: AF26, AF27 The following pins must be connected to XGND_SRDS2: • SD2_RX[3:0] • SD2_RX[3:0] MPC8572E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 5 Freescale Semiconductor System Design Information 133 ...

Page 134

... MT/s DDR data rate 0x80E8_0022) SEC included AUL = E = Ver. 2.2.1 1333-MHz processor; 667 MT/s DDR data rate 0x80E0_0022) SEC not ATL = included 1200-MHz processor; 667 MT/s DDR data rate ARL = 1067-MHz processor; 667 MT/s DDR data rate Freescale Semiconductor r Silicon (SVR = (SVR = ...

Page 135

... PPC Blank = Not included Notes: 1 MPC stands for “Qualified.” PPC stands for “Prototype” 2 See Section 18, “Package Description,” MPC8572E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 5 Freescale Semiconductor t l Package Temperature Power Sphere Type Blank = –40 to 105°C Standard ...

Page 136

... Table 89. Meaning of Last Line of Part Marking MPC8572E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 5 136 Figure 67. MPC8572xxxxxx MMMMM CCCCC ATWLYYWW FC-PBGA Figure 67. Part Marking for FC-PBGA Device 67. Digit Description A Assembly Site E Oak Hill Q KLM WL Lot number YY Year assembled WW Work week assembled Freescale Semiconductor ...

Page 137

... Section 22.1, “Part Numbers Fully Addressed by this Document,” Table 88 0 07/2008 • Initial release. MPC8572E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 5 Freescale Semiconductor Table 90. Document Revision History Substantive Change(s) Table 4, “MPC8572E Power Dissipation,” to include low power product. 86, “Part Numbering Nomenclature—Rev 2.2.1.” ...

Page 138

... Freescale Semiconductor product could create a situation where personal injury or death may occur. Should Buyer ...