MPC8572EPXAVND Freescale Semiconductor, MPC8572EPXAVND Datasheet - Page 73

• Manufacturer Part Number: MPC8572EPXAVND
• Description: MPU POWERQUICC III 1023-PBGA
• Manufacturer: Freescale Semiconductor

Specifications of MPC8572EPXAVND

• Processor Type: MPC85xx PowerQUICC III 32-Bit
• Speed: 1.5GHz
• Voltage: 1.1V
• Mounting Type: Surface Mount
• Package / Case: 1023-FCPBGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Features: -

To illustrate these definitions using real values, consider the case of a CML (Current Mode Logic)
transmitter that has a common mode voltage of 2.25 V and each of its outputs, TD and TD, has a swing
that goes between 2.5 V and 2.0 V. Using these values, the peak-to-peak voltage swing of each signal (TD
or TD) is 500 mV p-p, which is referred as the single-ended swing for each signal. In this example, because
the differential signaling environment is fully symmetrical, the transmitter output’s differential swing
(V
between 500 mV and –500 mV, in other words, V
phase. The peak differential voltage (V
is 1000 mV p-p.
15.2
The SerDes reference clock inputs are applied to an internal PLL whose output creates the clock used by
the corresponding SerDes lanes. The SerDes reference clocks inputs are SD1_REF_CLK and
SD1_REF_CLK for PCI Express and Serial RapidIO, or SD2_REF_CLK and SD2_REF_CLK for the
SGMII interface respectively.
The following sections describe the SerDes reference clock requirements and some application
information.
15.2.1
Figure 44
follows:
Freescale Semiconductor
OD
•
•
) has the same amplitude as each signal’s single-ended swing. The differential output signal ranges
A Volts
B Volts
The supply voltage requirements for XV
SerDes Reference Clock Receiver Reference Circuit Structure
— The SDn_REF_CLK and SDn_REF_CLK are internally AC-coupled differential inputs as
SerDes Reference Clocks
shows a receiver reference diagram of the SerDes reference clocks. Characteristics are as
shown in
on-chip 50-Ω termination to SGND_SRDSn (xcorevss) followed by on-chip AC-coupling.
SerDes Reference Clock Receiver Characteristics
MPC8572E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 5
Figure 43. Differential Voltage Definitions for Transmitter or Receiver
Figure
SDn_TX or
SDn_RX
SDn_TX or
SDn_RX
44. Each differential clock input (SDn_REF_CLK or SDn_REF_CLK) has
Differential Peak-Peak Voltage, V
DIFFp
Differential Swing, V
Differential Peak Voltage, V
) is 500 mV. The peak-to-peak differential voltage (V
DD_SRDS2
OD
is 500 mV in one phase and –500 mV in the other
are specified in
ID
or V
DIFFpp
OD
DIFFp
= 2*V
= A – B
= |A – B|
DIFFp
Table 1
(not shown)
High-Speed Serial Interfaces (HSSI)
and
V
cm
Table
= (A + B) / 2
2.
DIFFp-p
73
)