Z8S18020FEC Zilog, Z8S18020FEC Datasheet - Page 41

• Manufacturer Part Number: Z8S18020FEC
• Description: IC Z180 MPU 80-QFP
• Manufacturer: Zilog

Specifications of Z8S18020FEC

• Processor Type: Z180
• Features: Enhanced Z180
• Speed: 20MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 80-BQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: 269-3103

to
ZiLOG
Data can be written into and read from the ASCI Transmit
Data Register. If data is read from the ASCI Transmit Data
Register, the ASCI data transmit operation is not affected
by this
receives data shifted in on the
automatically transferred to the ASCI Receive Data Regis-
ter (
incoming data byte is shifted in, an overrun error occurs.
This register is not program accessible.
This four-entry
Rx Overrun, and Break status bits associated with each char-
features a multiprocessor communication mode that utilizes
an extra data bit for selective communication when a num-
ber of processors share a common serial bus. Multiproces-
sor data format is selected when the
is selected,
follows. If
multiprocessor bit (
flags. Effectively, other bytes (with
by the ASCI. If
1
. If multiprocessor mode is not selected (
) if it is empty. If
),
operation.
is set to
enables or disables the
has no effect. If multiprocessor mode
contains Parity Error, Framing Error,
is reset to
1
)
, only received bytes in which the
can affect the
is not empty when the next
0
, all bytes, regardless of
pin. When full, data is
bit in
wake-up
This register
T h e A S C I
) are
feature as
and error
ignored
bit in
is set
register. When a complete incoming data byte is assembled
in
ceive Data First-In First-Out (
character in the
Data Register (
shifted into
ceiver is well buffered.
acter in the receive data
acter (if any) can be read from the ASCI status registers.
the state of the
transmitter is enabled. When
is disables and any transmit operation in progress is inter-
rupted. However, the
contents of
mode during
ASCI receiver is enabled. When
mitter is disabled and any transmit operation in progress is
interrupted. However, the
is cleared to
, it is automatically transferred to the 4 character Re-
The ASCI Receive Data Register is a read-only
while the
0
are held.
data bit, affect the
). The next incoming data byte can be
during
.
(if any) can be read from the Receive
flag is not reset and the previous
. The status of the oldest char-
When
is cleared to
is reset to
flag is not reset and the pre-
is full. Thus, the ASCI re-
When
.
) memory. The oldest
is reset to
is set to
0
, the transmitter
is set to
and error flags.
0
0
1
in
, the trans-
, the ASCI
1
, the