Z8S18020FEC Zilog, Z8S18020FEC Datasheet - Page 54

• Manufacturer Part Number: Z8S18020FEC
• Description: IC Z180 MPU 80-QFP
• Manufacturer: Zilog

Specifications of Z8S18020FEC

• Processor Type: Z180
• Features: Enhanced Z180
• Speed: 20MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 80-BQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: 269-3103

The DMA Destination Address Register Channel 0
specifies the physical destination address for channel 0
transfers. The register contains 20 bits and can specify up
to 1024-KB memory addresses or up to 64-KB I/O
addresses. Channel 0 destination can be memory, I/O, or
memory mapped I/O. For I/O, the
identify the Request Handshake signal for channel 0.
bits of this register
If the DMA destination is in I/O space, bits
ister select the DMA request signal for DMA0, as follows:
of this reg-
ZiLOG