EZ80L92AZ050SC Zilog, EZ80L92AZ050SC Datasheet - Page 182

• Manufacturer Part Number: EZ80L92AZ050SC
• Description: IC WEBSERVER 50MHZ 100LQFP
• Manufacturer: Zilog

Specifications of EZ80L92AZ050SC

• Processor Type: eZ80
• Features: High Speed, Single-Cycle Instruction-Fetch
• Speed: 50MHz
• Voltage: 3.3V
• Mounting Type: Surface Mount
• Package / Case: 100-LQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: 269-3170; EZ80L92AZ050SC

PS013014-0107
Note:
Instruction Store 4:0 Registers
The ZDI Instruction Store registers are located in the ZDI Register Write-Only address
space. They can be written with instruction data for direct execution by the CPU. When
the ZDI_IS0 register is written, the eZ80L92 exits the ZDI BREAK state and executes a
single instruction. The Op Codes and operands for the instruction come from these
Instruction Store registers. The Instruction Store Register 0 is the first byte fetched,
followed by Instruction Store registers 1, 2, 3, and 4, as necessary.
Only the bytes the processor requires to execute the instruction must be stored in these
registers. Some eZ80 instructions, when combined with the MEMORY mode suffixes
(.SIS, .SIL, .LIS, or .LIL), require 6 bytes to operate. These 6-byte instructions cannot be
executed directly using the ZDI Instruction Store registers. See
The Instruction Store 0 register is located at a higher ZDI address than the other
tion Store
tion to load and execute a multibyte instruction with a single data stream from the ZDI
master. Execution of the instruction commences with writing the final byte to ZDI_IS0.
Bit
Position
7
ZDI_BUSAK_EN
6
ZDI_BUSAK
[5:0]
registers. This feature allows the use of the ZDI auto-address increment func-
000000 Reserved.
Value Description
0
1
0
1
Bus requests by external peripherals using the BUSREQ
pin are ignored. The bus acknowledge signal, BUSACK, is
not asserted in response to any bus requests.
Bus requests by external peripherals using the BUSREQ
pin are accepted. A bus acknowledge occurs at the end of
the current ZDI operation. The bus acknowledge is
indicated by asserting the BUSACK pin in response to a
bus request.
Deassert the bus acknowledge pin (BUSACK) to return
control of the address and data buses back to ZDI.
Assert the bus acknowledge pin (BUSACK) to pass control
of the address and data buses to an external peripheral.
Table
Product Specification
ZiLOG Debug Interface
98.
eZ80L92 MCU
Instruc-
176