N80960SB16 Intel, N80960SB16 Datasheet - Page 6

• Manufacturer Part Number: N80960SB16
• Description: IC MPU I960SB 16MHZ 84-PLCC
• Manufacturer: Intel

Specifications of N80960SB16

• Rohs Status: RoHS non-compliant
• Processor Type: i960
• Features: SB suffix, 32-Bit, 512 Byte Cache
• Speed: 16MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 84-PLCC
• Other names: 803883

80960SB
1.1
The 80960SB architecture is based on the most
recent advances in microprocessor technology and
is grounded in Intel’s long experience in the design
and manufacture of embedded microprocessors.
Many features contribute to the 80960SB’s excep-
tional performance:
2
1. Large Register Set. Having a large number of
2. Fast Instruction Execution. Simple functions
3. Load/Store Architecture. One way to improve
4. Simple Instruction Formats. All instructions
registers reduces the number of times that a
processor needs to access memory. Modern
compilers can take advantage of this feature to
optimize execution speed. For maximum flexi-
bility, the 80960SB provides thirty-two 32-bit
registers and four 80-bit floating point registers.
(See Figure 2.)
make up the bulk of instructions in most
programs so that execution speed can be
improved by ensuring that these core instruc-
tions are executed as quickly as possible. The
most frequently executed instructions — such
as
logical operations and shifts — execute in one
to two cycles. (Table 1 contains a list of instruc-
tions.)
execution speed is to reduce the number of
times that the processor must access memory
to perform an operation. As with other
processors based on RISC technology, the
80960SB has a Load/Store architecture. As
such, only the LOAD and STORE instructions
reference
operate on registers. This type of architecture
simplifies instruction decoding and is used in
combination with other techniques to increase
parallelism.
in the 80960SB are 32 bits long and must be
aligned on word boundaries. This alignment
makes it possible to eliminate the instruction
alignment stage in the pipeline. To simplify the
instruction
instruction formats; each instruction uses only
one format. (See Figure 3.)
Key Performance Features
register-register
memory;
decoder,
all
there
moves,
other
are
add/subtract,
instructions
only
five
5. Overlapped Instruction Execution. Load
6. Integer Execution Optimization. When the
7. Bandwidth Optimizations. The 80960SB gets
8. Cache Bypass. If a cache miss occurs, the
operations allow execution of subsequent
instructions to continue before the data has
been returned from memory, so that these
instructions
80960SB manages this process transparently
to software through the use of a register score-
board. Conditional instructions also make use
of a scoreboard so that subsequent unrelated
instructions may be executed while the condi-
tional instruction is pending.
result of an arithmetic execution is used as an
operand in a subsequent calculation, the value
is sent immediately to its destination register.
At the same time, the value is put on a bypass
path to the ALU, thereby saving the time that
otherwise would be required to retrieve the
value for the next operation.
optimal use of its memory bus bandwidth
because the bus is tuned for use with the on-
chip instruction cache: instruction cache line
size matches the maximum burst size for
instruction fetches. The 80960SB automatically
fetches four words in a burst and stores them
directly in the cache. Due to the size of the
cache and the fact that it is continually filled in
anticipation of needed instructions in the
program flow, the 80960SB is relatively insen-
sitive to memory wait states. The benefit is that
the 80960SB delivers outstanding performance
even with a low cost memory system.
processor fetches the needed instruction then
sends it on to the instruction decoder at the
same time it updates the cache. Thus, no extra
time is spent to load and read the cache.
can
overlap
the
load.
The