FW80200M733SL678 Intel, FW80200M733SL678 Datasheet - Page 16

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FW80200M733SL678

Manufacturer Part Number
FW80200M733SL678
Description
IC I/O PROCESSOR 733MHZ 241-BGA
Manufacturer
Intel
Datasheet

Specifications of FW80200M733SL678

Rohs Status
RoHS non-compliant
Processor Type
I/O
Features
XScale Core
Speed
733MHz
Voltage
5V
Mounting Type
Surface Mount
Package / Case
241-BGA
Other names
844850

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Package Information
Table 5.
16
®
80200 Processor based on Intel
JTAG Pins
TCK
TDI
TDO
TRST#
TMS
Name
January 2003
Count
1
1
1
1
1
®
XScale
Type
O
I
I
I
I
Datasheet - Commercial and Extended Temperature (80200T)
TEST CLOCK is an input which provides the clocking function for
the IEEE 1149.1 Boundary Scan Testing (JTAG). State information
and data are clocked into the component on the rising edge and
data is clocked out of the component on the falling edge.
TEST DATA INPUT is the serial input pin for the JTAG feature. TDI
is sampled on the rising edge of TCK, during the SHIFT-IR and
SHIFT-DR states of the Test Access Port. This signal has a weak
internal pullup to ensure proper operation when this signal is
unconnected.
TEST DATA OUTPUT is the serial output pin for the JTAG feature.
TDO is driven on the falling edge of TCK during the SHIFT-IR and
SHIFT-DR states of the Test Access Port. At other times, TDO
floats.
TEST RESET asynchronously resets the Test Access Port (TAP)
controller function of IEEE 1149.1 Boundary Scan Testing (JTAG).
This signal has a weak internal pullup to ensure proper operation
when this signal is unconnected.
TRST# must be driven low during processor reset to ensure proper
operation. Additionally, before performing JTAG test, the processor
should be reset and should have a valid clock at CLK to ensure it
does not enter a low-power mode.
TEST MODE SELECT is sampled at the rising edge of TCK to
select the operation of the test logic for IEEE 1149.1 Boundary
Scan testing. This signal has a weak internal pullup to ensure
proper operation when this signal is unconnected.
Microarchitecture
Description

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