EE80C188EB25

Manufacturer Part NumberEE80C188EB25
DescriptionIC MPU 16-BIT 5V 25MHZ 84-PLCC
ManufacturerIntel
EE80C188EB25 datasheet
 


Specifications of EE80C188EB25

Processor Type80C188FeaturesEB suffix, 16-Bit, Extended Temp
Speed25MHzVoltage5V
Mounting TypeSurface MountPackage / Case84-PLCC
Lead Free Status / RoHS StatusLead free / RoHS CompliantOther names864077
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80C186EB/80C188E B AND 80L186EB/80L188EB
16-BIT HIGH-INTEGRATION EMBEDDED PROCESSORS
True CMOS Inputs and Outputs
Integrate d Feature Set
— Low-Power Static CPU Core
— Two Independent UARTs each with
an Integral Baud Rate Generator
— Two 8-Bit Multiplexed I/ O Ports
— Programmable Interrupt Controller
— Three Programmable 16-Bit
Timer/Counters
— Clock Generator
— Ten Programmable Chip Selects with
Integral Wait-State Generator
— Memory Refresh Control Unit
— System Level Testing Support (ONCE
Mode)
Direct Addressing Capability to 1 Mbyte
Memory and 64 Kbyte I/O
Speed Versions Available (5V):
— 25 MHz (80C186EB25/80C188EB25)
— 20 MHz (80C186EB20/80C188EB20)
— 13 MHz (80C186EB13/80C188EB13)
The 80C186EB is a second generation CHMOS High-Integration microprocessor. It has features that are new
to the 80C186 family and include a STATIC CPU core, an enhanced Chip Select decode unit, two independent
Serial Channels, I/O ports, and the capability of Idle or Powerdown low power modes.
* Other brands and names are the property of their respective owners.
Information in this document is provided in connection with Intel products. Intel assumes no liability whatsoever, including infringement of any patent or
copyright, for sale and use of Intel products except as provided in Intel’s Terms and Conditions of Sale for such products. Intel retains the right to make
changes to these specifications at any time, without notice. Microcomputer Products may have minor variations to this specification known as errata.
COPYRIGHT © INTEL CORPORATION, 2004
Full Static Operation
Available in Extended Temperature
-
°
Range (
40
C to
Speed Versions Available (3V):
— 16 MHz (80L186EB16/80L188EB16)
— 13 MHz (80L186EB13/80L188EB13)
Low-Power Operating Modes:
—Idle Mode Freezes CPU Clocks but
keeps Peripherals Active
—Powerdown Mode Freezes All
Internal Clocks
Supports 80C187 Numeric Coprocessor
Interface (80C186EB PLCC Only)
Available In:
—80-Pin Quad Flat Pack (QFP)
—84-Pin Plastic Leaded Chip Carrier
(PLCC)
—80-Pin Shrink Quad Flat Pack (SQFP)
July, 2004
+
°
85
C)
272433– 1
Order Number: 272433-006

EE80C188EB25 Summary of contents

  • Page 1

    ... Information in this document is provided in connection with Intel products. Intel assumes no liability whatsoever, including infringement of any patent or copyright, for sale and use of Intel products except as provided in Intel’s Terms and Conditions of Sale for such products. Intel retains the right to make changes to these specifications at any time, without notice. Microcomputer Products may have minor variations to this specification known as errata. ...

  • Page 2

    High-Integration Embedded Processors CONTENTS INTRODUCTION CORE ARCHITECTURE Bus Interface Unit Clock Generator 80C186EC PERIPHERAL ARCHITECTURE Interrupt Control Unit Timer Counter Unit Serial Communications Unit Chip-Select Unit I O Port Unit Refresh Control Unit Power ...

  • Page 3

    NOTE Pin names in parentheses apply to the 80C188EB 80L188EB Figure 1 80C186EB 80C188EB Block Diagram 80C186EB 80C188EB 80L186EB 80L188EB 272433 – ...

  • Page 4

    INTRODUCTION Unless specifically noted all references to the 80C186EB apply to the 80C188EB 80L186EB and 80L188EB References to pins that differ between the 80C186EB 80L186EB and the 80C188EB 80L188EB are given in parentheses The ‘‘L’’ in ...

  • Page 5

    Crystal Connection NOTE The L C network is only required when using a third overtone crystal The following parameters are recommended when choosing a crystal Temperature Range Application Specific ESR (Equivalent Series Resistance) C0 (Shunt Capacitance of ...

  • Page 6

    PCB PCB Function Offset Offset 00H Reserved 40H 02H End Of Interrupt 42H Timer2 Compare 04H Poll 44H 06H Poll Status 46H Timer2 Control 08H Interrupt Mask 48H 0AH Priority Mask 4AH 0CH In-Service 4CH 0EH ...

  • Page 7

    Serial Communications Unit The Serial Control Unit (SCU) of the 80C186EB con- tains two independent channels Each channel is identical in operation except that only channel 0 is supported by the integrated interrupt controller (channel 1 has an external interrupt ...

  • Page 8

    ... Leaded Chip Carrier (PLCC) package, Shrink Quad Flat Pack (SQFP), and Quad Flat Pack (QFP) pack- age. For complete package specifications and infor- mation, see the Intel Packaging Outlines and Dimen- sions Guide (Order Number: 231369). Prefix Identification With the extended temperature range, operational ...

  • Page 9

    Table 2 Pin Description Nomenclature Symbol P Power Pin (Apply G Ground (Connect Input Only Pin O Output Only Pin I O Input Output Pin S(E) Synchronous Edge Sensitive S(L) Synchronous Level Sensitive A(E) Asynchronous Edge Sensitive ...

  • Page 10

    Pin Pin Input Output Name Type Type States CLKIN I A(E) OSCOUT O H(Q) R(Q) P(Q) CLKOUT O H(Q) R(Q) P(Q) RESIN I A(L) RESOUT O H(0) R(1) PDTMR I ...

  • Page 11

    Table 3 Pin Descriptions (Continued) Pin Pin Input Output Name Type Type States A18 A(L) H(Z) A19 ONCE R(WH) (A15 A8) P(X) (A18 16) (A19 ONCE H(Z) R(Z) P(1) ALE O H(0) R(0) P(0) ...

  • Page 12

    Table 3 Pin Descriptions (Continued) Pin Pin Input Output Name Type Type States H(Z) R(Z) LOCK O H(Z) R(WH) HOLD I A(L) HLDA O NCS ERROR I A(L) (N ...

  • Page 13

    Table 3 Pin Descriptions (Continued) Pin Pin Input Name Type Type T0OUT O T1OUT T0IN I A(L) T1IN A(E) INT0 I A(E L) INT1 INT4 INT2 INTA0 I O A(E L) INT3 INTA1 A( ...

  • Page 14

    PINOUT Tables 4 and 5 list the 80C186EB 80C188EB pin names with package location for the 84-pin Plastic Leaded Chip Carrier (PLCC) component Figure 5 depicts the complete 80C186EB 80C188EB pinout (PLCC package) as viewed ...

  • Page 15

    Table 5 PLCC Package Locations with Pin Name Location Name Location ERROR ( ALE 27 7 BHE (RFSH ...

  • Page 16

    NOTE: This is the FPO number location (indicated by X’s). Pin names in parentheses apply to the 80C188EB/80L188EB. Figure 4. 84-Pin Plastic Leaded Chip Carrier Pinout Diagram 16 272433– 5 ...

  • Page 17

    Table 6 QFP Pin Name with Package Location Address Data Bus Bus Control Name Location Name AD0 10 ALE AD1 15 BHE (RFSH) AD2 17 S0 AD3 19 S1 AD4 21 S2 AD5 23 RD AD6 25 WR AD7 27 ...

  • Page 18

    Table 7 QFP Package Location with Pin Names Location Name Location 1 CTS0 21 2 TXD0 22 3 RXD0 BCLK0 SINT1 CTS1 26 7 ...

  • Page 19

    NOTE: This is the FPO number location (indicated by X’s). Pin names in parentheses apply to the 80C188EB/80L188EB. Figure 5. Quad Flat Pack Pinout Diagram 80C186EB/80C188EB, 80L186EB/80L188EB 272433– ...

  • Page 20

    Table 8 SQFP Pin Functions with Location AD Bus Bus Control AD0 47 ALE AD1 52 BHE (RFSH ) AD2 54 S0 AD3 56 S1 AD4 58 S2 AD5 60 RD AD6 62 WR AD7 64 ...

  • Page 21

    ... NOTE: XXXXXXXXC indicates Intel FPO number. Pin names in parentheses apply to the 80C188EB/80L188EB. 80C186EB/80C188EB, 80L186EB/80L188EB Figure 6. SQFP Package 272433– ...

  • Page 22

    PACKAGE THERMAL SPECIFICATIONS The 80C186EB 80L186EB is specified for operation when T (the case temperature) is within the range 100 C (PLCC package 114 C (QFP package) T ...

  • Page 23

    ELECTRICAL SPECIFICATIONS Absolute Maximum Ratings Storage Temperature Case Temp under Bias Supply Voltage with Respect Voltage on other Pins with Respect ...

  • Page 24

    DC SPECIFICATIONS (80C186EB 80C188EB) Symbol Parameter V Supply Voltage CC V Input Low Voltage IL V Input High Voltage IH V Output Low Voltage OL V Output High Voltage OH V Input Hysterisis on RESIN HYR ...

  • Page 25

    DC SPECIFICATIONS (80L186EB16) Symbol Parameter V Supply Voltage CC V Input Low Voltage IL V Input High Voltage IH V Output Low Voltage OL V Output High Voltage OH V Input Hysterisis on RESIN HYR I Input Leakage Current for ...

  • Page 26

    DC SPECIFICATIONS (80L186EB13 80L188EB13 Symbol Parameter V Supply Voltage CC V Input Low Voltage IL V Input High Voltage IH V Output Low Voltage OL V Output High Voltage OH V Input Hysterisis on RESIN HYR ...

  • Page 27

    I VERSUS FREQUENCY AND VOLTAGE CC The current (I ) consumption of the processor is CC essentially composed of two components I I CCS I is the quiescent current that represents internal PD device leakage and is measured with all ...

  • Page 28

    AC SPECIFICATIONS AC Characteristics 80C186EB25 Symbol Parameter INPUT CLOCK T CLKIN Frequency F T CLKIN Period C T CLKIN High Time CH T CLKIN Low Time CL T CLKIN Rise Time CR T CLKIN Fall Time ...

  • Page 29

    AC SPECIFICATIONS AC Characteristics 80C186EB25 Symbol SYNCHRONOUS INPUTS T TEST NMI INT4 0 BCLK1 0 T1 0IN READY CTS1 CHIS T TEST NMI INT4 0 BCLK1 0 T1 0IN READY CTS1 0 CHIH T AD15 ...

  • Page 30

    AC SPECIFICATIONS AC Characteristics 80C186EB20 80C186EB13 Symbol Parameter INPUT CLOCK T CLKIN Frequency F T CLKIN Period C T CLKIN High Time CH T CLKIN Low Time CL T CLKIN Rise Time CR T CLKIN Fall ...

  • Page 31

    AC SPECIFICATIONS AC Characteristics 80C186EB20 80C186EB13 Symbol Parameter SYNCHRONOUS INPUTS T TEST NMI INT4 0 BCLK1 0 T1 0IN CHIS READY CTS1 TEST NMI INT4 0 BCLK1 0 T1 0IN CHIH READY CTS1 0 ...

  • Page 32

    AC SPECIFICATIONS AC Characteristics 80L186EB16 Symbol Parameter INPUT CLOCK T CLKIN Frequency F T CLKIN Period C T CLKIN High Time CH T CLKIN Low Time CL T CLKIN Rise Time CR T CLKIN Fall Time ...

  • Page 33

    AC SPECIFICATIONS AC Characteristics 80L186EB16 Symbol SYNCHRONOUS INPUTS T TEST NMI INT4 0 BCLK1 0 T1 0IN READY CTS1 CHIS T TEST NMI INT4 0 T1 0IN BCLK1 0 READY CTS1 0 CHIH T AD15 ...

  • Page 34

    AC SPECIFICATIONS AC Characteristics 80L186EB13 Symbol Parameter INPUT CLOCK T CLKIN Frequency r T CLKIN Period C T CLKIN High Time CH T CLKIN Low Time CL T CLKIN Rise Time CR T CLKIN Fall Time ...

  • Page 35

    AC SPECIFICATIONS AC Characteristics 80L186EB13 80L186EB8 Symbol Parameter SYNCHRONOUS INPUTS T TEST, NMI, INT4:0, CHIS BCLK1 0 T1 0IN READY CTS1 TEST, NMI, INT4:0, T1:0IN, CHIH BCLK1 0 READY CTS1 0 T AD15:0 (AD7:0), ...

  • Page 36

    AC SPECIFICATIONS (Continued) Relative Timings (80C186EB25 20 13 80L186EB16 13 8) Symbol Parameter RELATIVE TIMINGS T ALE Rising to ALE Falling LHLL T Address Valid to ALE Falling AVLL T Chip Selects Valid to ALE Falling ...

  • Page 37

    AC SPECIFICATIONS (Continued) Serial Port Mode 0 Timings (80C186EB25 20 13 80L186EB16 13 8) Symbol Parameter T TXD Clock Period XLXL T TXD Clock Low to Clock High (n XLXH T TXD Clock Low to Clock High (n XLXH T ...

  • Page 38

    AC TEST CONDITIONS The AC specifications are tested with the 50 pF load shown in Figure 7 See the Derating Curves section to see how timings vary with load capacitance Specifications are measured at the V ...

  • Page 39

    NOTE 20% V Float 80 Figure 9 Output Delay and Float Waveform Figure 10 Input Setup and Hold 80C186EB 80C188EB 80L186EB 80L188EB 272433 –10 272433 –11 39 ...

  • Page 40

    NOTE Pin names in parentheses apply to 80C188EB 80L188EB Figure 11 Relative Signal Waveform Figure 12 Serial Port Mode 0 Waveform 40 272433 –12 272433 –13 ...

  • Page 41

    DERATING CURVES TYPICAL OUTPUT DELAY VARIATIONS VERSUS LOAD CAPACITANCE TYPICAL RISE AND FALL VARIATIONS VERSUS LOAD CAPACITANCE 80C186EB 80C188EB 80L186EB 80L188EB 272433 –14 Figure 13 272433 –15 Figure 14 41 ...

  • Page 42

    RESET The processor will perform a reset operation any time the RESIN pin active The RESIN pin is actually synchronized before it is presented internally which means that the clock must be operating before a reset ...

  • Page 43

    Figure 15 Cold Reset Waveforms 43 ...

  • Page 44

    Figure 16 Warm Reset Waveforms 44 ...

  • Page 45

    BUS CYCLE WAVEFORMS Figures 17 through 23 present the various bus cy- cles that are generated by the processor What is shown in the figure is the relationship of the various NOTE Pin names in parentheses apply to 80C188EB 80L188EB ...

  • Page 46

    NOTE Pin names in parentheses apply to 80C188EB 80L188EB Figure 18 Write Cycle Waveforms 46 272433 –19 ...

  • Page 47

    NOTE The address driven is typically the location of the next instruction prefetch Under a majority of instruction sequences the AD15 0 (AD7 0) bus will float while the A19 16 (A19 8) bus remains driven and all bus control ...

  • Page 48

    NOTE Pin names in parentheses apply to 80C188EB 80L188EB Figure 20 Interrupt Acknowledge Cycle Waveform 48 272433 –21 ...

  • Page 49

    NOTE Pin names in parentheses apply to 80C188EB 80L188EB Figure 21 HOLD HLDA Waveforms 80C186EB 80C188EB 80L186EB 80L188EB 272433 –22 49 ...

  • Page 50

    NOTES 1 READY must be low by either edge to cause a wait state 2 Lighter lines indicate READ cycles darker lines indicate WRITE cycles Pin names in parentheses apply to 80C188EB 80L188EB Figure 22 Refresh ...

  • Page 51

    NOTES 1 READY must be low by either edge to cause a wait state 2 Lighter lines indicate READ cycles darker lines indicate WRITE cycles Pin names in parentheses apply to 80C188EB 80L188EB Figure 23 Ready Waveforms 80C186EB 80C188EB 80L186EB ...

  • Page 52

    EXECUTION TIMINGS A determination of program execution timing must consider the bus cycles necessary to prefetch in- structions as well as the number of execution unit cycles necessary to execute instructions The fol- lowing instruction timings ...

  • Page 53

    INSTRUCTION SET SUMMARY Function DATA TRANSFER MOV Move e Register to Register Memory Register memory to register Immediate to register memory ...

  • Page 54

    INSTRUCTION SET SUMMARY Function DATA TRANSFER (Continued) SEGMENT Segment Override ...

  • Page 55

    INSTRUCTION SET SUMMARY Function ARITHMETIC (Continued) IMUL Integer multiply (signed Register-Byte Register-Word Memory-Byte Memory-Word IMUL Integer Immediate multiply (signed) DIV Divide (unsigned) ...

  • Page 56

    INSTRUCTION SET SUMMARY Function LOGIC (Continued) XOR Exclusive or e Reg memory and register to either Immediate to register memory ...

  • Page 57

    INSTRUCTION SET SUMMARY Function CONTROL TRANSFER (Continued) RET Return from CALL e Within segment Within seg adding immed Intersegment ...

  • Page 58

    INSTRUCTION SET SUMMARY Function PROCESSOR CONTROL CLC Clear carry CMC Complement carry STC Set carry ...

  • Page 59

    ERRATA An 80C186EB 80L186EB with a STEPID value of 0001H has the following known errata A device with a STEPID of 0001H can be visually identified by the presence of an ‘‘A’’ alpha character next to the FPO number The ...