PRIXP422BB Intel, PRIXP422BB Datasheet - Page 35

• Manufacturer Part Number: PRIXP422BB
• Description: IC NETWRK PROCESSR 266MHZ 492BGA
• Manufacturer: Intel

Specifications of PRIXP422BB

• Processor Type: Network
• Features: XScale Core
• Speed: 266MHz
• Voltage: 1.3V
• Mounting Type: Surface Mount
• Package / Case: 492-BGA
• Core Operating Frequency: 533MHz
• Package Type: BGA
• Pin Count: 492
• Mounting: Surface Mount
• Operating Temperature (max): 85C
• Operating Temperature (min): -40C
• Operating Temperature Classification: Industrial
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 869384

Specification Clarifications
1.
Issue:
Implication:
Affected Docs:
2.
Issue:
Implication:
Affected Docs:
3.
Issue:
Intel
®
IXP42X Product Line of Network Processors and IXC1100 Control Plane Processor
PCI Byte Enables All Asserted During All Memory Cycle Reads (SCR 1897)
The PCI controller drives all byte enables low (asserted) during a memory cycle read of
non-prefetch memory. However, I/O reads and memory-cycle writes do drive individual byte
enables.
If an external PCI device has non-prefetch memory and requires either a 16-bit or 8-bit read, there
is a possibility that the device will not respond correctly to the IXP42X product line and IXC1100
control plane processors’ memory reads. This is because the IXP42X product line and IXC1100
control plane processors always perform a 32-bit read to the non-prefetch memory region specified
in register PCI_NP_AD.
The 8-bit or 16-bit external device should respond with a “target abort,” as per the PCI 2.2
specification, if a 32-bit read is performed to its non-prefetch memory and it requires a 16-bit or
8-bit read.
The IXP42X product line and IXC1100 control plane processors will drive all the byte enables
asserted during all memory cycle reads of the external PCI device, no matter what the
PCI_NP_CBE register contains in the byte enable bits.
To read non-prefetch memory sub-DWORDS (8-bit or 16-bit), use I/O reads. If it is necessary to
use memory cycle reads of sub-DWORDS, a hardware work around may be required. Contact your
Intel field application engineer if you require a hardware work around.
Intel
fication (11725, v. 1.0) and the Intel
Control Plane Processor Developer’s Manual (252480)
Pull-Up Resistor Required on ETH_MDIO Pin (SCR 1225)
An external pull-up resistor of 1.5K ohm is required on ETH_MDIO to properly quantify the
external PHYs used in the system. For specific implementation specifics, see the IEEE 802.3 speci-
fication.
Incorrect number of PHYs will be identified. For example, when interfacing a single Intel
LXT972 Fast Ethernet Transceiver to one of the IXP42X product line and IXC1100 control plane
processors — without the external resistor — the processor will see 32 PHYs on the MII interface.
Intel
Datasheet (252479-002)
Ethernet MAC Broadcast Disable bit Needs Further Documentation (SCR 4166)
Section 15.1.5 of the Intel
Plane Processor Developer’s Manual states “Determining if the 48-bit destination address of the
received frame contains all logic 1s, filters the broadcast frames. Setting bit 7 of Receive Control
Register 1 (RXCTRL1) to logic 1 prevents received broadcast frames from being sent to the NPE.”
Section 15.2.3 further documents Bit 7, Broadcast Disable. 1 = Prevents broadcast packets from
being passed to the application logic.
®
®
IXP425 Network Processor Based on Intel
IXP42X Product Line of Network Processors and IXC1100 Control Plane Processor
®
IXP42X Product Line of Network Processors and IXC1100 Control
®
IXP42X Product Line of Network Processors and IXC1100
®
XScale™ Microarchitecture Component Speci-
Specification Clarifications
35
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