MC68020RC20E Freescale Semiconductor, MC68020RC20E Datasheet - Page 109

• Manufacturer Part Number: MC68020RC20E
• Description: IC MICROPROCESSOR 32BIT 114-PGA
• Manufacturer: Freescale Semiconductor

Specifications of MC68020RC20E

• Processor Type: M680x0 32-Bit
• Speed: 20MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 114-PGA
• Family Name: M68000
• Device Core: ColdFire
• Device Core Size: 32b
• Frequency (max): 20MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 5V
• Operating Supply Voltage (max): 5.25V
• Operating Supply Voltage (min): 4.75V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Through Hole
• Pin Count: 114
• Package Type: PGA
• Lead Free Status / RoHS Status: Contains lead / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: Compliant

Freescale Semiconductor, Inc.
5.6 BUS SYNCHRONIZATION
The MC68020/EC020 overlaps instruction execution—that is, during bus activity for one
instruction, instructions that do not use the external bus can be executed. Due to the
independent operation of the on-chip cache relative to the operation of the bus controller,
many subsequent instructions can be executed, resulting in seemingly nonsequential
instruction execution. When this is not desired and the system depends on sequential
execution following bus activity, the NOP instruction can be used. The NOP instruction
forces instruction and bus synchronization by freezing instruction execution until all
pending bus cycles have completed.
An example of the use of the NOP instruction for this purpose is the case of a write
operation of control information to an external register in which the external hardware
attempts to control program execution based on the data that is written with the
conditional assertion of BERR. Since the MC68020/EC020 cannot process the bus error
until the end of the bus cycle, the external hardware has not successfully interrupted
program execution. To prevent a subsequent instruction from executing until the external
cycle completes, the NOP instruction can be inserted after the instruction causing the
write. In this case, bus error exception processing proceeds immediately after the write
and before subsequent instructions are executed. This is an irregular situation, and the
use of the NOP instruction for this purpose is not required by most systems.
5.7 BUS ARBITRATION
The bus design of the MC68020/EC020 provides for a single bus master at any one time:
either the processor or an external device. One or more of the external devices on the bus
can have the capability of becoming bus master. Bus arbitration is the protocol by which
an external device becomes bus master; the bus controller in the MC68020/EC020
manages the bus arbitration signals so that the processor has the lowest priority.
Bus arbitration differs in the MC68020 and MC68EC020 due to the absence of BGACK in
the MC68EC020. Because of this difference, bus arbitration of the MC68020 and
MC68EC020 is discussed separately.
External devices that need to obtain the bus must assert the bus arbitration signals in the
sequences described in 5.7.1 MC68020 Bus Arbitration or 5.7.2 MC68EC020 Bus
Arbitration. Systems having several devices that can become bus master require
external circuitry to assign priorities to the devices, so that when two or more external
devices attempt to become bus master at the same time, the one having the highest
priority becomes bus master first.
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M68020 USER’S MANUAL
MOTOROLA
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