MC8640DVU1067NC Freescale Semiconductor, MC8640DVU1067NC Datasheet - Page 122

• Manufacturer Part Number: MC8640DVU1067NC
• Description: MPU DUAL E600 1023-FCCBGA
• Manufacturer: Freescale Semiconductor

Specifications of MC8640DVU1067NC

• Processor Type: MPC86xx PowerPC 32-Bit
• Speed: 1.067GHz
• Voltage: 0.95V
• Mounting Type: Surface Mount
• Package / Case: 1023-FCCBGA
• Family Name: MC8xxx
• Device Core: PowerQUICC
• Device Core Size: 32b
• Frequency (max): 1.067GHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 0.95/1.05V
• Operating Supply Voltage (max): 1/1.1V
• Operating Supply Voltage (min): 0.9/1V
• Operating Temp Range: 0C to 105C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 1023
• Package Type: FCCBGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Features: -
• Lead Free Status / Rohs Status: Compliant

System Design Information
20.8
The MPC8640 provides the user with power-on configuration options which can be set through the use of
external pull-up or pull-down resistors of 4.7 kΩ on certain output pins (see customer visible configuration
pins). These pins are generally used as output only pins in normal operation.
While HRESET is asserted however, these pins are treated as inputs. The value presented on these pins
while HRESET is asserted, is latched when HRESET deasserts, at which time the input receiver is disabled
and the I/O circuit takes on its normal function. Most of these sampled configuration pins are equipped
with an on-chip gated resistor of approximately 20 kΩ. This value should permit the 4.7-kΩ resistor to pull
the configuration pin to a valid logic low level. The pull-up resistor is enabled only during HRESET (and
for platform/system clocks after HRESET deassertion to ensure capture of the reset value). When the input
receiver is disabled, the pull-up is also, thus allowing functional operation of the pin as an output with
minimal signal quality or delay disruption. The default value for all configuration bits treated this way has
been encoded such that a high voltage level puts the device into the default state and external resistors are
needed only when non-default settings are required by the user.
Careful board layout with stubless connections to these pull-down resistors coupled with the large value
of the pull-down resistor should minimize the disruption of signal quality or speed for output pins thus
configured.
The platform PLL ratio and e600 PLL ratio configuration pins are not equipped with these default pull-up
devices.
20.9
Correct operation of the JTAG interface requires configuration of a group of system control pins as
demonstrated in
state under normal operating conditions as most have asynchronous behavior and spurious assertion will
give unpredictable results.
Boundary-scan testing is enabled through the JTAG interface signals. The TRST signal is optional in the
IEEE 1149.1 specification, but is provided on all processors that implement the Power Architecture
technology. The device requires TRST to be asserted during reset conditions to ensure the JTAG boundary
logic does not interfere with normal chip operation. While it is possible to force the TAP controller to the
reset state using only the TCK and TMS signals, more reliable power-on reset performance will be obtained
if the TRST signal is asserted during power-on reset. Because the JTAG interface is also used for accessing
the common on-chip processor (COP) function, simply tying TRST to HRESET is not practical.
The COP function of these processors allows a remote computer system (typically a PC with dedicated
hardware and debugging software) to access and control the internal operations of the processor. The COP
port connects primarily through the JTAG interface of the processor, with some additional status
monitoring signals. The COP port requires the ability to independently assert HRESET or TRST in order
to fully control the processor. If the target system has independent reset sources, such as voltage monitors,
watchdog timers, power supply failures, or push-button switches, then the COP reset signals must be
merged into these signals with logic.
The arrangement shown in
while ensuring that the target can drive HRESET as well.
122
Configuration Pin Muxing
JTAG Configuration Signals
MPC8640 and MPC8640D Integrated Host Processor Hardware Specifications, Rev. 3
Figure
68. Care must be taken to ensure that these pins are maintained at a valid deasserted
Figure 67
allows the COP port to independently assert HRESET or TRST,
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