IC CODEC 4ADC/6DAC 24 BIT 52MQFP

AD1836AASZ

Manufacturer Part NumberAD1836AASZ
DescriptionIC CODEC 4ADC/6DAC 24 BIT 52MQFP
ManufacturerAnalog Devices Inc
TypeGeneral Purpose
AD1836AASZ datasheet
 


Specifications of AD1836AASZ

Data InterfaceSerialResolution (bits)24 b
Number Of Adcs / Dacs4 / 6Sigma DeltaYes
S/n Ratio, Adcs / Dacs (db) Typ105 / 108Dynamic Range, Adcs / Dacs (db) Typ105 / 108
Voltage - Supply, Analog4.75 V ~ 5.25 VVoltage - Supply, Digital4.75 V ~ 5.25 V
Operating Temperature-40°C ~ 85°CMounting TypeSurface Mount
Package / Case52-BQFPAudio Codec TypeStereo
No. Of Adcs4No. Of Dacs6
No. Of Input Channels4No. Of Output Channels6
Adc / Dac Resolution24bitAdcs / Dacs Signal To Noise Ratio108dB
Lead Free Status / RoHS StatusLead free / RoHS CompliantFor Use WithAD1836AZ-DBRD - BOARD EVAL FOR AD1836AAD1836A-DBRD - BOARD EVAL FOR AD1836A
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FEATURES
5 V multichannel audio system
Accepts 16-/18-/20-/24-bit data
Supports 24-bit and 96 kHz sample rate
Multibit Σ-∆ modulators with data directed
scrambling
Differential output for optimum performance
ADCs: –92 dB THD + N, 105 dB SNR and dynamic range
DACs: –95 dB THD + N, 108 dB SNR and dynamic range
On-chip volume control with "auto-ramp" function
Programmable gain amplifier for ADC input
Hardware and software controllable clickless mute
Digital de-emphasis processing
Supports 256 × f
, 512 × f
, or 768 × f
S
S
S
Power-down mode plus soft power-down mode
Flexible serial data port with right justified, left justified, I
compatible, and DSP serial port modes
TDM interface mode supports 8 in/8 out using a single
SHARC® SPORT
52-lead MQFP (PQFP) plastic package
DLRCLK
DBCLK
DSDATA1
DSDATA2
DSDATA3
ALRCLK
ABCLK
ASDATA1
ASDATA2
Σ-∆
ADC1L
ADC1L
48kHz/96kHz
Σ-∆
ADC1R
ADC1R
48kHz/96kHz
CAPL1
ADC2L1
PGA
ADC2L2
CAPL2
CAPR1
ADC2R1
PGA
ADC2R2
CAPR2
Rev. 0
Information furnished by Analog Devices is believed to be accurate and reliable.
However, no responsibility is assumed by Analog Devices for its use, nor for any
infringements of patents or other rights of third parties that may result from its use.
Specifications subject to change without notice. No license is granted by implication
or otherwise under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective owners.
APPLICATIONS
Home theater systems
Automotive audio systems
DVD recorders
Set-top boxes
Digital audio effects processors
PRODUCT OVERVIEW
The AD1836A is a high performance, single-chip codec that
provides three stereo DACs and two stereo ADCs using ADI’s
patented multibit Σ-∆ architecture. An SPI® port is included,
allowing a microcontroller to adjust volume and many other
parameters. The AD1836A operates from a 5 V supply, with
master clock
provision for a separate output supply to interface with low
voltage external circuitry. The AD1836A is available in a 52-lead
2
S
MQFP (PQFP) package.
FUNCTIONAL BLOCK DIAGRAM
CCLK
CDATA CLATCH
COUT
CONTROL PORT
SERIAL
DATA
I/O
VOLUME
PORT
VOLUME
DIGITAL
VOLUME
FILTER
48kHz/96kHz
VOLUME
DIGITAL
FILTER
48kHz/96kHz
VOLUME
Σ-∆
VOLUME
DIGITAL
ADC2L
FILTER
48kHz
48kHz
Σ-∆
DIGITAL
ADC2R
FILTER
48kHz
48kHz
2
PD/RST
AVDD
Figure 1.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
Fax: 781.326.8703
Multichannel 96 kHz Codec
AD1836A
MCLK
CLOCK
DAC1L
DIGITAL
Σ-∆
FILTER
DAC
DAC1R
DAC2L
DIGITAL
Σ-∆
FILTER
DAC
DAC2R
DAC3L
DIGITAL
Σ-∆
FILTER
DAC
DAC3R
FILTD
V
FILTR
REF
4
3
2
AGND
DVDD
DGND
www.analog.com
© 2003 Analog Devices, Inc. All rights reserved.

AD1836AASZ Summary of contents

  • Page 1

    FEATURES 5 V multichannel audio system Accepts 16-/18-/20-/24-bit data Supports 24-bit and 96 kHz sample rate Multibit Σ-∆ modulators with data directed scrambling Differential output for optimum performance ADCs: –92 dB THD + N, 105 dB SNR and dynamic range ...

  • Page 2

    AD1836A TABLE OF CONTENTS AD1836A—Specifications ............................................................... 3 Absolute Maximum Ratings............................................................ 8 Pin Configuration And Pin Functional Descriptions.................. 9 Functional Overview...................................................................... 11 ADCs............................................................................................ 11 DACs ............................................................................................ 11 Clock Signals ............................................................................... 11 Reset and Power-Down ............................................................. 12 REVISION HISTORY Revision 0: Initial ...

  • Page 3

    AD1836A—SPECIFICATIONS Table 1. Test conditions, unless otherwise noted. Performance of all channels is identical (exclusive of the Interchannel Gain Mismatch and Interchannel Phase Deviation specifications). Parameter Supply Voltages (AVDD, DVDD) Ambient Temperature Master Clock Input Signal Input Sample Rate Measurement ...

  • Page 4

    AD1836A Table 2. Analog Performance Parameter ANALOG-TO-DIGITAL CONVERTERS DIGITAL-TO-ANALOG CONVERTERS 1 Total harmonic distortion + noise and dynamic range typical specifications are for two channels active, max/min are all channels active. 2 Measured with Audio Precision System Two Cascade in ...

  • Page 5

    Table 3. Digital I/O Parameter Input Voltage Input Voltage Input Leakage ( 2 Input Leakage ( 0 High Level Output ...

  • Page 6

    AD1836A Table 7. Timing Specifications Parameter MASTER CLOCK AND RESET SPI PORT DAC SERIAL PORT (Normal Modes) DAC SERIAL PORT (Packed 128 Mode, Packed 256 Mode) ADC SERIAL PORT (Normal Modes) ADC SERIAL PORT (Packed 128 Mode, Packed 256 Mode) ...

  • Page 7

    Table 7. Timing Specifications (Continued) Parameter AUXILIARY INTERFACE (Master Mode) AUXILIARY INTERFACE (Slave Mode) Comments t AUXBCLK Delay From MCLK Transition, 256 × f XBD From MCLK Rising, 512 × AUXLRCLK Skew From AUXBCLK Falling XLS t AUXBCLK ...

  • Page 8

    AD1836A ABSOLUTE MAXIMUM RATINGS Table 8. AD1836A Absolute Maximum Ratings Parameter Analog (AVDD) Digital (DVDD) Input Current (Except Supply Pins) Analog Input Voltage (Signal Pins) Digital Input Voltage (Signal Pins) Ambient Temperature (Operating) Stresses above those listed under Absolute Maximum ...

  • Page 9

    PIN CONFIGURATION AND PIN FUNCTIONAL DESCRIPTIONS OUTLP3 OUTLN3 OUTLP2 OUTLN2 OUTLP1 OUTLN1 Table 10. Pin Function Descriptions—52-Lead MQFP Pin No. In/Out Mnemonic 1 I DVDD 2 I CDATA 3 I PD/RST 4 O OUTLP3 5 O OUTLN3 6 O OUTLP2 ...

  • Page 10

    AD1836A Pin No. In/Out Mnemonic 27 I ADC2INRP/CAPR2 28 I AGND 29 I AGND 30 O OUTRN1 31 O OUTRP1 32 O OUTRN2 33 O OUTRP2 34 O OUTRN3 35 O OUTRP3 36 I/O DLRCLK 37 I/O DBCLK 38 I ...

  • Page 11

    FUNCTIONAL OVERVIEW ADCs There are four ADC channels in the AD1836A configured as two independent stereo pairs. One stereo pair is the primary ADC and has fully differential inputs. The second pair can be programmed to operate in one of ...

  • Page 12

    AD1836A through an FPGA or other large digital chip before being applied to the AD1836A. In most cases, this will induce clock jitter due to the fact that the clock signal is sharing common power and ground connections with other ...

  • Page 13

    POWER SUPPLY AND VOLTAGE REFERENCE The AD1836A is designed for 5 V supplies. Separate power supply pins are provided for the analog and digital sections. These pins should be bypassed with 100 nF ceramic chip capacitors, as close to the ...

  • Page 14

    AD1836A LRCLK LEFT CHANNEL BCLK SDATA MSB LEFT CHANNEL LRCLK BCLK MSB SDATA LEFT CHANNEL LRCLK BCLK MSB SDATA LRCLK BCLK SDATA MSB NOTES 1. DSP MODE DOES NOT IDENTIFY CHANNEL 2. LRCLK NORMALLY OPERATES BCLK FREQUENCY ...

  • Page 15

    LRCLK 128 BCLKs BCLK 32 BCLKs SLOT 1 SLOT 2 DATA LEFT 0 LEFT 1 MSB MSB–1 MSB–2 Figure 5. ADC Packed Mode 128 LRCLK 256 BCLKs BCLK 32 BCLKs SLOT 1 SLOT 2 DATA SLOT 3 SLOT 4 LEFT ...

  • Page 16

    AD1836A FSTDM BCLK TDM MSB TDM ASDATA1 1ST CH TDM (OUT) INTERNAL ASDATA1 ADC L0 32 MSB TDM DSDATA1 1ST CH TDM (IN) INTERNAL DSDATA1 DAC L0 32 AUX 2 LRCLK I S (FROM AUX ADC NO. 1) AUX 2 ...

  • Page 17

    LRCLK BCLK ADC NO. 1 SLAVE DATA MCLK LRCLK DLRCLK/AUXLRCLK BCLK DSDATA2/AAUXDATA1 ADC NO. 2 SLAVE DATA DSDATA3/AAUXDATA2 MCLK MCLK Figure 10. AUX Mode Connection to SHARC (Master Mode) 30MHz 12.288MHz LRCLK BCLK ADC NO. 1 MASTER DATA ...

  • Page 18

    AD1836A Table 11. Pin Function Changes in AUX Mode 2 2 Pin Name (I S/AUX Mode Mode 2 ASDATA1( Data Out, Internal ADC1 ASDATA2(O)/DAUXDATA( Data Out, Internal ADC2 2 DSDATA1( Data ...

  • Page 19

    SPI CONTROL REGISTERS Note that all control registers default to zero at power-up. Table 12. Serial SPI Word Format Register Address 15:12 4 Bits Table 13. Register Addresses and Functions Register Address Bit 15 Bit 14 Bit 13 Bit 12 ...

  • Page 20

    AD1836A Table 15. DAC Control Register 2 Address RD/WR Reserved 15, 14 0001 0 00000 Table 16. DAC Volume Registers Address RD/WR 15, 14, 13 0010: DAC1L 0 0011: DAC1R ...

  • Page 21

    Table 19. ADC Control Register 3 When changing clock mode, other SPI bits that are written during the same SPI transaction may be lost. Therefore recommended that these be set separately. Address RD/WR Reserved Clock Mode 15, 14, ...

  • Page 22

    AD1836A INPUT NO. 1 INPUT NO. 2 NOTE ADC2 SINGLE-ENDED MUX PGA INPUT MODE––LEFT CHANNEL ONLY SHOWN. CONTROL REGISTER 3 CONTENTS: 6 LSBs: SELECT INPUT NO 1010 LEFT + VE LEFT – VE AD1836A CAP1L C1 1nF – ...

  • Page 23

    OUTLINE DIMENSIONS SEATING PLANE VIEW A ESD CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although this product features proprietary ESD ...

  • Page 24

    AD1836A NOTES © 2003 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. C03800–0–8/03(0) Rev Page ...