LM4546BVHX/NOPB National Semiconductor, LM4546BVHX/NOPB Datasheet
LM4546BVHX/NOPB
Specifications of LM4546BVHX/NOPB
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LM4546BVHX/NOPB Summary of contents
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... Output Frames. The AC ’97 architecture separates the analog and digital functions of the PC audio system allowing both for system design flexibility and increased performance. © 2006 National Semiconductor Corporation Key Specifications n Analog Mixer Dynamic Range n DAC Dynamic Range n ADC Dynamic Range Features n AC ’ ...
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... Absolute Maximum Ratings If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/ Distributors for availability and specifications. Supply Voltage Storage Temperature Input Voltage ESD Susceptibility (Note 2) pin 3 ESD Susceptibility (Note 3) pin 3 Junction Temperature Electrical Characteristics Sampling Frequency (Fs kHz, single codec configuration, (primary mode) unless otherwise noted. Limits apply for T 25˚ ...
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Electrical Characteristics Sampling Frequency (Fs kHz, single codec configuration, (primary mode) unless otherwise noted. Limits apply for T 25˚C. The reference for Vrms unless otherwise specified. (Continued) Symbol Parameter Analog to Digital Converters Resolution ...
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Electrical Characteristics Sampling Frequency (Fs kHz, single codec configuration, (primary mode) unless otherwise noted. Limits apply for T 25˚C. The reference for Vrms unless otherwise specified. (Continued) Symbol Parameter T Output Valid Delay CO ...
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Timing Diagrams Clocks Digital Rise and Fall www.national.com Data Delay, Setup and Hold 20123310 20123312 Power On Reset Cold Reset Warm Reset 6 20123311 Legend 20123330 20123329 20123313 20123314 ...
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Typical Application FIGURE 1. LM4546B Typical Application Circuit, Single Codec, 1 Vrms inputs APPLICATION HINTS • The LM4546B must be initialized by using RESET# to perform a Power-On-Reset as shown in the Power On Reset Timing Diagram • Don’t leave ...
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Connection Diagram Pin Descriptions Name Pin Functional Description Mono Input This line level (1 Vrms nominal) mono input is mixed equally into both channels of the Stereo Mix signal at MIX2 under the control of the PC_Beep ...
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Pin Descriptions (Continued) Name Pin Functional Description AC Ground Reference This input is the reference for the signals on both CD_L and CD_R. CD_GND is NOT a DC ground and should be AC-coupled to the stereo source ...
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Pin Descriptions (Continued) Name Pin Functional Description Left Stereo Channel Output This line level output (1 Vrms nominal) is fed from the left channel of the Stereo Mix signal LINE_OUT_L 35 O from MIX2 via the Master ...
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Pin Descriptions (Continued) Name Pin Link frame marker and Warm Reset This input defines the boundaries of AC Link frames. Each frame lasts 256 periods of BIT_CLK. In normal operation SYNC kHz positive ...
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Pin Descriptions (Continued) 3D SOUND AND NO-CONNECTS (NC) (Continued) Name Pin 14–17 These pins are not used and should be left open (NC). 29– For second source applications these pins may be connected to a ...
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Volume Output Volume www.national.com Input Sources ADC 14 ...
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Functional Description GENERAL The LM4546B codec can mix, process and convert among analog (stereo and mono) and digital (AC Link format) inputs and outputs. There are two stereo and four mono analog inputs and one stereo and one mono analog ...
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AC Link Serial Interface Protocol AC LINK OUTPUT FRAME: SDATA_OUT, CONTROLLER OUTPUT TO LM4546B INPUT The AC Link Output Frame carries control and PCM data to the LM4546B control registers and stereo DAC. Output Frames are carried on the SDATA_OUT ...
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AC Link Serial Interface Protocol (Continued) checks the valid-data bits for 4 slots. In Primary mode these tag bits are for: slot 1 (Command Address), slot 2 (Command Data), slot 3 (PCM data for left DAC) and slot 4 (PCM ...
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AC Link Serial Interface Protocol (Continued) SDATA_OUT: Slots – Reserved These slots are not used by the LM4546B and should all be stuffed with zeros by the AC ’97 Controller. AC LINK INPUT FRAME: SDATA_IN, CONTROLLER INPUT ...
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AC Link Serial Interface Protocol (Continued) SLOT 0, INPUT FRAME Bit Description Comment Codec Ready Link Interface Ready 15 Bit Slot 1 data 1 = Valid Status Address or 14 valid Slot Request Slot 2 data 1 ...
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AC Link Serial Interface Protocol (Continued) SDATA_IN: Slot 4 – PCM Record Right Channel This slot contains sampled data from the right channel of the stereo ADC. The signal to be digitized is selected using the Record Select register (1Ah) ...
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Register Descriptions Default settings are indicated by *. RESET REGISTER (00h) Writing any value to this register causes a Register Reset which changes all registers back to their default values read is performed on this register, the LM4546B ...
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Register Descriptions RECORD GAIN REGISTER (1Ch) This register controls the input levels for both channels of the stereo ADC. The inputs come from the Record Select Mux and are selected via the Record Select Control register, 1Ah. The gain of ...
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Register Descriptions Pin 46 Pin 45 D15,28h D14,28h (ID1) (ID0) (ID1) (ID0) GND NC/ GND GND 1 1 EXTENDED AUDIO STATUS/CONTROL REGISTER (2Ah) This read/write register provides status and control of the variable sample rate capabilities in ...
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Low Power Modes (Continued) Improving System Performance The audio codec is capable of dynamic range performance in excess of 90 db., but the user must pay careful attention to several factors to achieve this. A primary consideration is keeping analog ...
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Multiple Codecs (Continued) The Identity control pins, ID1, ID0 (pins 46 and 45) are internally pulled The Codec may therefore be DD configured as ’Primary’ either by leaving ID1, ID0 open (NC strapping them ...
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Multiple Codecs (Continued) FIGURE 9. Multiple Codecs using Extended AC Link Test Modes AC ’97 Rev 2.1 defines two test modes: ATE test mode and Vendor test mode. Cold Reset is the only way to exit either of them. The ...
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