STTS424E02CDA6F STMicroelectronics, STTS424E02CDA6F Datasheet - Page 36

• Manufacturer Part Number: STTS424E02CDA6F
• Description: Board Mount Temperature Sensors MEM Module Temp Sens 2Kb SPD
• Manufacturer: STMicroelectronics

Specifications of STTS424E02CDA6F

• Full Temp Accuracy: +/- 3 C
• Package / Case: DFN EP
• Digital Output - Bus Interface: Serial (2-Wire, I2C)
• Digital Output - Number Of Bits: 10 bit
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: - 40 C
• Output Type: Analog
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Use in a memory module
6
6.1
6.1.1
6.1.2
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Use in a memory module
In the dual inline memory module (DIMM) application, the SPD is soldered directly on to the
printed circuit module. The three chip enable inputs (A0, A1, A2) must be connected to V
or V
socket (see
The write control (WC) of the device is tied to ground to maintain full read and write access.
Table 24.
Programming the SPD
The situations in which the SPD EEPROM is programmed can be considered under two
headings:
●
●
DIMM isolated
With specific programming equipment, it is possible to define the SPD EEPROM content,
using byte and page write instructions, and its write-protection using the SWP and CWP
instructions. To issue the SWP and CWP instructions, the DIMM must be inserted in the
application-specific slot where the A0 signal can be driven to V
instruction. This programming step is mainly intended for use by DIMM makers, whose end
application manufacturers will want to clear this write-protection with the CWP on their own
specific programming equipment, to modify the lower 128 bytes, and finally to set
permanently the write-protection with the PSWP instruction.
DIMM inserted in the application motherboard
As the final application cannot drive the A0 pin to V
the write-protection with the PSWP instruction.
DD
when the DIMM is isolated (not inserted on the PCB motherboard)
when the DIMM is inserted on the PCB motherboard
directly (that is without using a pull-up or pull-down resistor) through the DIMM
DIMM position
Table
DRAM DIMM connections
0
1
2
3
4
5
6
7
24).
Doc ID 13448 Rev 8
V
V
V
V
V
V
V
V
SS
SS
SS
DD
DD
DD
DD
SS
A2
(0)
(0)
(0)
(0)
(1)
(1)
(1)
(1)
HV
, the only possible action is to freeze
V
V
V
V
V
V
V
V
DD
DD
DD
DD
SS
SS
SS
SS
A1
(0)
(0)
(1)
(1)
(0)
(0)
(1)
(1)
HV
during the whole
STTS424E02
V
V
V
V
V
V
V
V
DD
DD
DD
SS
SS
SS
SS
DD
A0
(1)
(0)
(1)
(0)
(0)
(1)
(0)
(1)
SS