E-ETC5054D-X/HTR STMicroelectronics, E-ETC5054D-X/HTR Datasheet

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E-ETC5054D-X/HTR

Manufacturer Part Number
E-ETC5054D-X/HTR
Description
IC CODEC/FILTER SERIAL 16-SOIC
Manufacturer
STMicroelectronics
Type
PCM Codec/Filterr
Datasheet

Specifications of E-ETC5054D-X/HTR

Data Interface
Serial
Resolution (bits)
8 b
Number Of Adcs / Dacs
1 / 2
Sigma Delta
No
Voltage - Supply, Analog
4.75 V ~ 5.25 V
Operating Temperature
-25°C ~ 125°C
Mounting Type
Surface Mount
Package / Case
16-SOIC (0.300", 7.50mm Width)
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
497-1108-2
ETC5054D-X/HTR

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Part Number:
E-ETC5054D-X/HTR
Manufacturer:
ST
0
March 2000
This is advanced information on a new product now in development or undergoing evaluation. Details are subject to change without notice.
DESCRIPTION
The ETC5057/ETC5054 family consists of A-law
and –law monolithic PCM CODEC/filters utilizing
the A/D and D/A conversion architecture shown in
the block diagram below, and a serial PCM inter-
face. The devices are fabricated using double-
poly CMOS process. The encode portion of each
device consists of an input gain adjust amplifier,
an active RC pre-filter which eliminates very high
frequency noise prior to entering a switched-ca-
pacitor band-pass filter that rejects signals below
200 Hz and above 3400 Hz. Also included are
auto-zero circuitry and a companding coder which
samples the filtered signal and encodes it in the
companded A-law or –law PCM format. The de-
code portion of each device consists of an ex-
panding decoder, which reconstructs the analog
signal from the companded A-law or –law code,
a low-pass filter which corrects for the sin x/x re-
sponse of the decoder output and rejects signals
above 3400 Hz and is followed by a single-ended
power amplifier capable of driving low impedance
loads. The devices require 1.536 MHz, 1.544
COMPLETE CODEC AND FILTERING SYS-
TEM (DEVICE) INCLUDING:
– Transmit high-pass and low-pass filtering.
– Receive low-pass filter with sin x/x correction.
– Active RC noise filters
– -law or A-law compatible COder and DECoder.
– Internal precision voltage reference.
– Serial I/O interface.
– Internal auto-zero circuitry.
A-LAW 16 PINS (ETC5057FN, 20 PINS)
(ETC5054FN, 20 PINS)
MEETS OR EXCEEDS ALL D3/D4 AND
CCITT SPECIFICATIONS
LOW OPERATING POWER - TYPICALLY 60
mW
POWER-DOWN STANDBY MODE - TYPI-
CALLY 3 mW
AUTOMATIC POWER-DOWN
TTL OR CMOS COMPATIBLE DIGITAL IN-
TERFACES
MAXIMIZES LINE INTERFACE CARD CIR-
CUIT DENSITY
0 to 70 C OPERATION
-LAW WITHOUT SIGNALING, 16 PINS
5V OPERATION
®
SERIAL INTERFACE CODEC/FILTER
MHz, or 2.048 MHz transmit and receive master
clocks, which may be asynchronous, transmit and
receive bit clocks which may vary from 64 kHz to
2.048 MHz, and transmit and receive frame sync
pulses. The timing of the frame sync pulses and
PCM data is compatible with both industry stand-
ard formats.
ORDERING NUMBERS:
ORDERING NUMBERS:
ORDERING NUMBERS:
DIP16 (Plastic)
SO16 (Wide)
ETC5057FN
ETC5054FN
ETC5057D
ETC5054D
ETC5057N
ETC5054N
PLCC20
ETC5054
ETC5057
1/18

Related parts for E-ETC5054D-X/HTR

E-ETC5054D-X/HTR Summary of contents

Page 1

... Hz and is followed by a single-ended power amplifier capable of driving low impedance loads. The devices require 1.536 MHz, 1.544 March 2000 This is advanced information on a new product now in development or undergoing evaluation. Details are subject to change without notice. SERIAL INTERFACE CODEC/FILTER ORDERING NUMBERS: ORDERING NUMBERS: ORDERING NUMBERS: MHz ...

Page 2

... ETC5054 - ETC5057 PIN CONNECTIONS (Top view) DIP and SO BLOCK DIAGRAM 2/18 PLCC ...

Page 3

... Transmit Frame Enables BCLK Sync Pulse an 8 kHz pulse train. See figures 1, 2 and 3 for timing details. Transmit Time Slot Open drain output which pulses low during the encoder time slot. Recommended to be grounded if not used. Gain Set Analog output of the transmit input amplifier. Used to set gain externally ...

Page 4

... LONG FRAME SYNC OPERATION To use the long frame mode, both the frame sync pulses, FS clock periods long, with timing relationships speci- Selected fied in figure 3. Based on the transmit frame sync, ETC5054 FS , the device will sense whether short or long X frame sync pulses are being used. For 64 kHz op- 1 ...

Page 5

... Upon the occurence the data at the D R falling edge of the next eight BCLK riods. At the end of the decoder time slot, the de- coding cycle begins, and 10 s later the decoder DAC output is updated. The total decoder delay ) of nominally 2. (decoder update) plus 110 s (filter delay) plus 62 ...

Page 6

... ETC5054 - ETC5057 ANALOG INTERFACE WITH TRANSMIT INPUT AMPLIFIER (all devices) Symbol I XA Input Leakage Current I (–2.5V V +2.5V Input Resistance I (–2.5V V +2.5V Output Resistance (closed loop, unity gain Load Resistance Load Capacitance Output Dynamic Range ( Voltage Gain ( Unity Gain Bandwidth Offset Voltage ...

Page 7

... LSTTL loads) XDP X t Minimum Width of the Frame Sync Pulse (low level) WFL 64kbit/s operating mode) Note 1: For short frame sync timing FS X Figure 1: 64kbits/s TIMING DIAGRAM (see next page for complete timing). FSx FS R Parameter /CLKSEL Pin R MCLK and MCLK ...

Page 8

... ETC5054 - ETC5057 Figure 2: Short Frame Sync Timing 8/18 ...

Page 9

... Figure 3: Long Frame Sync Timing ETC5054 - ETC5057 9/18 ...

Page 10

... Transmit Gain, Relative to GXA 180 200 300 Hz - 3000 3300 3400 4000 4600 Hz and up, Measure Response from 4000 Hz G Absolute Transmit Gain Variation with Temperature XAT + Absolute Transmit Gain Variation with Supply Voltage XAV ( Transmit Gain Variations with Level XRL Sinusoidal Test Method Reference Level = – ...

Page 11

... XP N Receive Noise, P Message Weighted RP (A LAW, PCM code equals positive zero) N Transmit Noise, C Message Weighted XC N Receive Noise, C Message Weighted RC ( LAW, PCM Code Equals Alternating Positive and Negative Zero) N Noise, Single Frequency kHz to 100 kHz, Loop around Measurement Vrms X PPSR ...

Page 12

... Frequencies in the Range 300Hz - 3400Hz CROSSTALK Symbol CT Transmit to Receive Crosstalk, 0 dBm0 Transmit Level X 300Hz to 3400Hz Receive to Transmit Crosstalk, 0 dBm0 Receive Level R 300Hz to 3400Hz, (note 2) Notes: 1) Measured by extrapolation from distortion test results. 2) PPSR , NPSR , CT is measured with a –50dBm0 activating signal applied R-X ENCODING FORMAT ( +Full-scale ( ...

Page 13

... It may be necessary to use unequal values for the arms of the attenuators to achieve a precise attenuation. Generally it is tol- erable to allow a small deviation of the input im- pedance from nominal while still maintaining a good return loss ...

Page 14

... ETC5054 - ETC5057 Figure 6: Typical Synchronous Application. 14/18 ...

Page 15

... E 7.4 7.6 0.291 e 1. 10.65 0.394 h 0.25 0.75 0.010 L 0.4 1.27 0.016 K 0˚ (min.)8˚ (max inch TYP. MAX. 0.104 0.012 0.020 0.013 0.413 0.299 0.050 0.419 0.030 0.050 ETC5054 - ETC5057 OUTLINE AND MECHANICAL DATA SO16 Wide 15/18 ...

Page 16

... ETC5054 - ETC5057 mm DIM. MIN. TYP. MAX. a1 0.51 B 0.77 1.65 b 0 8.5 e 2.54 e3 17.78 F 7.1 I 5.1 L 3.3 Z 1.27 16/18 inch MIN. TYP. MAX. 0.020 0.030 0.065 0.020 0.010 0.787 0.335 0.100 0.700 0.280 0.201 0.130 0.050 OUTLINE AND MECHANICAL DATA DIP16 ...

Page 17

... D 4.2 4.57 0.165 d1 2.54 d2 0.56 E 7.37 8.38 0.290 e 1.27 F 0.38 G 0.101 M 1. PLCC20ME inch MECHANICAL DATA TYP. MAX. 0.395 0.356 0.180 0.100 0.022 0.330 0.050 0.015 0.004 0.050 0.045 (Seating Plane Coplanarity) ETC5054 - ETC5057 OUTLINE AND PLCC20 17/18 ...

Page 18

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