CP2201-GM Silicon Laboratories Inc, CP2201-GM Datasheet - Page 18

• Manufacturer Part Number: CP2201-GM
• Description: IC ETH CTRLR SNGL-CHIP 28QFN
• Manufacturer: Silicon Laboratories Inc

Specifications of CP2201-GM

• Package / Case: 48-TQFP, 48-VQFP
• Controller Type: Ethernet Controller, MAC/10Base-T
• Interface: Parallel/Serial
• Voltage - Supply: 3.1 V ~ 3.6 V
• Current - Supply: 75mA
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Ethernet Connection Type: 1000BASE-T or 100BASE-T or 10BASE-T
• Minimum Operating Temperature: - 40 C
• Mounting Style: SMD/SMT
• Product: Ethernet Controllers
• Standard Supported: IEEE 802.3
• Data Rate: 10 Mbps or 100 Mbps or 1000 Mbps
• Maximum Operating Temperature: + 85 C
• No. Of Ports: 1
• Ethernet Type: IEEE 802.3
• Interface Type: Parallel
• Supply Current: 60mA
• Supply Voltage Range: 3.1V To 3.6V
• Operating Temperature Range: -40°C To +85°C
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 336-1326 - KIT REF DESIGN PWR OVER ETHERNET336-1316 - KIT EVAL FOR CP2201 ETH CTRLR
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 336-1313

CP2200/1
6. Functional Description
6.1. Overview
In most systems, the CP2200/1 is used for transmitting and receiving Ethernet packets, non-volatile data storage,
and controlling Link and Activity LEDs. The device is controlled using direct and indirect internal registers
accessible through the parallel host interface. All digital pins on the device are 5 V tolerant.
6.2. Reset Initialization
After every CP2200/1 reset, the following initialization procedure is recommended to ensure proper device
operation:
6.3. Interrupt Request Signal
The CP2200/1 has an interrupt request signal (INT) that can be used to notify the host processor of pending
interrupts. The INT signal is asserted upon detection of any enabled interrupt event. Host processors that cannot
dedicate a port pin to the INT signal can periodically poll the interrupt status registers to see if any interrupt
generating events have occurred. If the /INT signal is not used, pending interrupts such a Receive FIFO Full must
still be serviced.
The 14 interrupt sources are listed below. Interrupts are enabled on reset and can be disabled by software.
Pending interrupts can be cleared (allowing the INT signal to de-assert) by reading the self-clearing interrupt
registers. See “8. Interrupt Sources” on page 30 for a complete description of the CP2200/1 interrupts.
18
End of Packet Reached
Receive FIFO Empty
Receive FIFO Full
Oscillator Initialization Complete
Self Initialization Complete
Flash Write/Erase Complete
Packet Transmitted
Step 1: Wait for the reset pin to rise. This step takes the longest during a power-on reset.
Step 2: Wait for Oscillator Initialization to complete. The host processor will receive notification through the
Step 3: Wait for Self Initialization to complete. The INT0 interrupt status register on page 31 should be
Step 4: Disable interrupts (using INT0EN and INT1EN on page 33 and page 36) for events that will not be
Step 5: Initialize the physical layer. See “15.7. Initializing the Physical Layer” on page 90 for a detailed
Step 6: Enable the desired Activity, Link, or Activity/Link LEDs using the IOPWR register on page 45.
Step 7: Initialize the media access controller (MAC). See “14.1. Initializing the MAC” on page 78 for a
Step 8: Configure the receive filter. See “12.4. Initializing the Receive Buffer, Filter and Hash Table” on
Step 9: The CP2200/1 is ready to transmit and receive packets.
interrupt request signal once the oscillator has stabilized.
checked to determine when Self Initialization completes.
monitored or handled by the host processor. By default, all interrupts are enabled after every reset.
physical layer initialization procedure.
detailed MAC initialization procedure.
page 59 for a detailed initialization procedure.
Rev. 1.0
Packet Received
“Wake-on-LAN” Wakeup Event
Link Status Changed
Jabber Detected
Auto-Negotiation Failed
Remote Fault Notification
Auto-Negotiation Complete